From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D3BFC433E0 for ; Fri, 22 May 2020 13:37:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 16B92207D8 for ; Fri, 22 May 2020 13:37:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="iS7m+eXd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729888AbgEVNhM (ORCPT ); Fri, 22 May 2020 09:37:12 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:41473 "EHLO esa4.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729406AbgEVNhM (ORCPT ); Fri, 22 May 2020 09:37:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1590154631; x=1621690631; h=date:from:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=EUWLCQ4b0qv6go+blgdo6JASANFDeUBjtKBjnvhD0WQ=; b=iS7m+eXd5st+hAlYEE7kUdTVnsmPtBDP4wB1XSlNhiw8me8bUFCixgJh x74A/eQvAQAzG1SnskWNV4ZjE2dl1wjvt5hTh8MylFEJwO7Zm+U+F9H+M CkfFlbPxFunoJk8TgG7jqZ4wyI0MFJ86Gqu3wYOWG1p5TMO3B1HTup1lw 11JyexZPnSkqt/Cs7sD2Gjl/MV9D1jPYip2NMkmYAP62pssJPBpU6Zecs qo9OeWjJnz3ovjaC2zlrKtT/CMrNsqmsUgD2WBtQ9D+odFOj+z/pVlD7r XZp7NlMdAmp+NVU6wVeoPpj6lpqHZeUhXBu3NyKOcYMQE1s0ESrsRvKga A==; IronPort-SDR: kd19uII32utgrXCJAuca0wveu56oQGsufOUMmtJfG9qflCrfqOPk6m9ayY/wrYlq/ZjY5DkosX izEAxqwCt7OT3/Nm5pYUVQf0VaMuDYJn1I8DUCSMjosBe3qpS5bCrjq0hXHgdh4mKOvraXOIqB 082Afx3ZUb8/Vg2TnEyRkwCZzwUfBB3KdDQzhBFizCRuLT/C/Id3tHvJJ6DjYZCTxG54jZLDMM Gdr21OKFYKWrXSPhiTrAZVSvwaoJkmVkMLQ91fhQey35JqYIT3bOddgzLaIce7Fk/oe5d8zhtP m/8= X-IronPort-AV: E=Sophos;i="5.73,421,1583164800"; d="scan'208";a="138318795" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 May 2020 21:37:11 +0800 IronPort-SDR: X3wqQbbFfA6vc6izKvMsy6zaniRREVJkLDVBDbVC1ac3HFr7P7vAEHcsVTZMN7PyUgnhbx53kZ CQTb+c8ldPjuvykXY+LhduN4y5FxSphj4= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2020 06:27:10 -0700 IronPort-SDR: 3BRm09RueVGL3LdWvuqgVbaRy3Bq4w4AF1j8jHdre2miVFDQ2hnA5GnX9SMWJyCqmuG7dZ4Dct ZCCYFXIASFEg== WDCIronportException: Internal Received: from unknown (HELO redsun52) ([10.149.66.28]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2020 06:37:09 -0700 Date: Fri, 22 May 2020 14:37:05 +0100 (BST) From: "Maciej W. Rozycki" To: Mikulas Patocka cc: Ivan Kokshaysky , "Maciej W. Rozycki" , Arnd Bergmann , Richard Henderson , Matt Turner , Greg Kroah-Hartman , alpha , linux-serial@vger.kernel.org, linux-rtc@vger.kernel.org Subject: Re: [PATCH 1/2 v3] alpha: add a delay to inb_p, inb_w and inb_l In-Reply-To: Message-ID: References: <20200513144128.GA16995@mail.rc.ru> User-Agent: Alpine 2.21 (LFD 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org On Fri, 22 May 2020, Mikulas Patocka wrote: > > Hmm, having barriers *afterwards* across all the MMIO accessors, even > > ones that do not have such a requirement according to memory-barriers.txt, > > does hurt performance unnecessarily however. What I think has to be done > > is adding barriers beforehand, and then only add barriers afterwards where > > necessary. Commit 92d7223a74 did a part of that, but did not consistently > > update all the remaining accessors. > > > > So I don't think reverting 92d7223a74 permanently is the right way to go, > > however it certainly makes sense to do that temporarily to get rid of the > > fatal regression, sort all the corner cases and then apply the resulting > > replacement fix. > > See Documentation/memory-barriers.txt, the section "KERNEL I/O BARRIER > EFFECTS" > > According to the specification, there must be a barrier before a write to > the MMIO space (paragraph 3) and after a read from MMIO space (parahraph > 4) - if this causes unnecessary slowdown, the driver should use > readX_relaxed or writeX_relaxed functions - the *_relaxed functions are > ordered with each other (see the paragraph "(*) readX_relaxed(), > writeX_relaxed()"), but they are not ordered with respect to memory > access. The specification doesn't require a barrier *after* a write however, which is what I have been concerned about as it may cost hundreds of cycles wasted. I'm not concerned about a barrier after a read (and one beforehand is of course also required). > The commit 92d7223a74 fixes that requirement (although there is no real > driver that was fixed by this), so I don't think it should be reverted. > The proper fix should be to add delays to the serial port and readltime > clock (or perhaps to all IO-port accesses). Adding artificial delays will only paper over the real problem I'm afraid. > > I think ultimately we do want the barriers beforehand, just like the > > MIPS port has (and survives) in arch/mips/include/asm/io.h. Observe > > If the MIPS port doesn't have MMIO barrier after read[bwl], then it is > violating the specification. Perhaps there is no existing driver that is > hurt by this violation, so this violation survived. It does have a barrier, see: /* prevent prefetching of coherent DMA data prematurely */ \ if (!relax) \ rmb(); \ In the light of #5 however: 5. A readX() by a CPU thread from the peripheral will complete before any subsequent delay() loop can begin execution on the same thread. I think it may have to be replaced with a completion barrier however, and that will be tricky because you cannot just issue a second read to the resource accessed after the `rmb' to make the first read complete, as a MMIO read may have side effects (e.g. clearing an interrupt request). So the read would have to happen to a different location. Some architectures have a hardware completion barrier instruction, such as the modern MIPS ISA, which makes life sweet and easy (as much as life can be sweet and easy with a weakly ordered bus model) as no dummy read is then required, but surely not all do (including older MIPS ISA revisions). Maciej