[MODERATED] Re: [patch V2 12/12] x86/apic: Ignore secondary threads if nosmt=force

[Linus Torvalds <torvalds@linux-foundation.org>]

On Wed, 6 Jun 2018, speck for Thomas Gleixner wrote:
> 
> nosmt=force makes the APIC detection code ignore the secondary SMT siblings
> completely, so they even do not show up as possible CPUs. This is more or
> less equivalent to disabling SMT in the BIOS.

So if we go down this route, I do think it should be very clearly 
documented that the BIOS disable can (and does) end up having resource 
allocation advantages that we cannot do in software later on.

The intel optimization manual is not very clear on what the partitioning 
rules are.

I find:

  "In general, the buffers for staging instructions between major pipe 
   stages  are partitioned. These buffers include µop queues after the  
   execution trace cache, the queues after the register rename stage, the
   reorder buffer which stages instructions for retirement, and the load 
   and store buffers.

   In the case of load and store buffers, partitioning also provided an 
   easier implementation to maintain memory ordering for each logical 
   processor and detect memory ordering violations"

but some of that partitioning may be relaxed if the HT thread is "not 
active":

  "In Intel microarchitecture code name Sandy Bridge, the micro-op queue 
   is statically partitioned to provide 28 entries for each logical 
   processor,  irrespective of software executing in single thread or 
   multiple threads. If one logical processor is not active in Intel 
   microarchitecture code name Ivy Bridge, then a single thread executing 
   on that processor  core can use the 56 entries in the micro-op queue"

but I do not know what "not active" means, and how dynamic it is. Some of 
that partitioning may be entirely static and depend on the early BIOS 
disabling of HT, and even if we park the cores, the resources will just be 
wasted.

From the above, it does sound like even if some of the instruction queues 
may be relaxed when one thread is idle (if that is what "not active") 
means, load and store buffers may be entirely statically partitioned. 

So I would really wanmt to have a big note along with the

  "This is more or less equivalent to disabling SMT in the BIOS"

because on some loads it might be a case of "less equivalent" than not.

               Linus