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* [PATCH] PCI: add quirk for 3ware 9650SE controller
@ 2013-08-27  9:44 Jiri Kosina
  2013-08-27  9:45 ` Jiri Kosina
  0 siblings, 1 reply; 14+ messages in thread
From: Jiri Kosina @ 2013-08-27  9:44 UTC (permalink / raw)
  To: Bjorn Helgaas, Adam Radford; +Cc: linux-kernel, linux-pci, linux-scsi

Commit d5dea7d95 ("PCI: msi: Disable msi interrupts when we initialize a 
pci device") makes MSIs be forcibly disabled at boot time.

It turns out that this breaks 3ware controller -- if MSIs are disabled 
during PCI discovery of this controller, the device doesn't work properly 
(it doesn't respond to any commands that are being sent to it after 
initialization).

Reverting d5dea7d95 or not force-disabling MSIs in pci_msi_init_pci_dev()
makes the device work properly again.

Signed-off-by: Jiri Kosina <jkosina@suse.cz>
---

I am adding Adam Radford as a recepient as well, to see whether he is able 
to provide some more explanation why this device would expose this 
behavior.
Thanks.

 drivers/pci/msi.c    |    3 +++
 drivers/pci/quirks.c |   10 ++++++++++
 include/linux/pci.h  |    1 +
 3 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index aca7578..4f36b8b 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -1040,6 +1040,9 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
 {
 	INIT_LIST_HEAD(&dev->msi_list);
 
+	if (dev->broken_msi_disable)
+		return;
+
 	/* Disable the msi hardware to avoid screaming interrupts
 	 * during boot.  This is the power on reset default so
 	 * usually this should be a noop.
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index e85d230..4ba3400 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2890,6 +2890,16 @@ static void quirk_intel_ntb(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
 
+/*
+ * 3ware 9650SE controller doesn't properly initialize if MSI are
+ * disabled on it during PCI device discovery
+ */
+static void quirk_broken_msi_disable(struct pci_dev *dev)
+{
+	dev->broken_msi_disable = 1;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_3WARE, 0x1004, quirk_broken_msi_disable);
+
 static ktime_t fixup_debug_start(struct pci_dev *dev,
 				 void (*fn)(struct pci_dev *dev))
 {
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 0fd1f15..c327d74 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -341,6 +341,7 @@ struct pci_dev {
 #ifdef CONFIG_PCI_MSI
 	struct list_head msi_list;
 	struct kset *msi_kset;
+	unsigned int	broken_msi_disable:1;
 #endif
 	struct pci_vpd *vpd;
 #ifdef CONFIG_PCI_ATS

-- 
Jiri Kosina
SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-08-27  9:44 [PATCH] PCI: add quirk for 3ware 9650SE controller Jiri Kosina
@ 2013-08-27  9:45 ` Jiri Kosina
  2013-08-28 15:46   ` Jiri Kosina
  0 siblings, 1 reply; 14+ messages in thread
From: Jiri Kosina @ 2013-08-27  9:45 UTC (permalink / raw)
  To: Bjorn Helgaas, Adam Radford
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman, Jesse Barnes


[ adding Bjorn and Eric to CC, sorry for omitting you originally ]

On Tue, 27 Aug 2013, Jiri Kosina wrote:

> Commit d5dea7d95 ("PCI: msi: Disable msi interrupts when we initialize a 
> pci device") makes MSIs be forcibly disabled at boot time.
> 
> It turns out that this breaks 3ware controller -- if MSIs are disabled 
> during PCI discovery of this controller, the device doesn't work properly 
> (it doesn't respond to any commands that are being sent to it after 
> initialization).
> 
> Reverting d5dea7d95 or not force-disabling MSIs in pci_msi_init_pci_dev()
> makes the device work properly again.
> 
> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
> ---
> 
> I am adding Adam Radford as a recepient as well, to see whether he is able 
> to provide some more explanation why this device would expose this 
> behavior.
> Thanks.
> 
>  drivers/pci/msi.c    |    3 +++
>  drivers/pci/quirks.c |   10 ++++++++++
>  include/linux/pci.h  |    1 +
>  3 files changed, 14 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
> index aca7578..4f36b8b 100644
> --- a/drivers/pci/msi.c
> +++ b/drivers/pci/msi.c
> @@ -1040,6 +1040,9 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
>  {
>  	INIT_LIST_HEAD(&dev->msi_list);
>  
> +	if (dev->broken_msi_disable)
> +		return;
> +
>  	/* Disable the msi hardware to avoid screaming interrupts
>  	 * during boot.  This is the power on reset default so
>  	 * usually this should be a noop.
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index e85d230..4ba3400 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2890,6 +2890,16 @@ static void quirk_intel_ntb(struct pci_dev *dev)
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
>  
> +/*
> + * 3ware 9650SE controller doesn't properly initialize if MSI are
> + * disabled on it during PCI device discovery
> + */
> +static void quirk_broken_msi_disable(struct pci_dev *dev)
> +{
> +	dev->broken_msi_disable = 1;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_3WARE, 0x1004, quirk_broken_msi_disable);
> +
>  static ktime_t fixup_debug_start(struct pci_dev *dev,
>  				 void (*fn)(struct pci_dev *dev))
>  {
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 0fd1f15..c327d74 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -341,6 +341,7 @@ struct pci_dev {
>  #ifdef CONFIG_PCI_MSI
>  	struct list_head msi_list;
>  	struct kset *msi_kset;
> +	unsigned int	broken_msi_disable:1;
>  #endif
>  	struct pci_vpd *vpd;
>  #ifdef CONFIG_PCI_ATS
> 
> -- 
> Jiri Kosina
> SUSE Labs
> 

-- 
Jiri Kosina
SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-08-27  9:45 ` Jiri Kosina
@ 2013-08-28 15:46   ` Jiri Kosina
  2013-08-28 16:33     ` Bjorn Helgaas
  0 siblings, 1 reply; 14+ messages in thread
From: Jiri Kosina @ 2013-08-28 15:46 UTC (permalink / raw)
  To: Bjorn Helgaas, Adam Radford
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman, Jesse Barnes

On Tue, 27 Aug 2013, Jiri Kosina wrote:

> On Tue, 27 Aug 2013, Jiri Kosina wrote:
> 
> > Commit d5dea7d95 ("PCI: msi: Disable msi interrupts when we initialize a 
> > pci device") makes MSIs be forcibly disabled at boot time.
> > 
> > It turns out that this breaks 3ware controller -- if MSIs are disabled 
> > during PCI discovery of this controller, the device doesn't work properly 
> > (it doesn't respond to any commands that are being sent to it after 
> > initialization).
> > 
> > Reverting d5dea7d95 or not force-disabling MSIs in pci_msi_init_pci_dev()
> > makes the device work properly again.
> > 
> > Signed-off-by: Jiri Kosina <jkosina@suse.cz>
> >
> > ---
> > 
> > I am adding Adam Radford as a recepient as well, to see whether he is able 
> > to provide some more explanation why this device would expose this 
> > behavior.

OK, so Adam Radford's lsi.com address is bouncing, hence I guess we can't 
expect any feedback from him.

Bjorn, Jesse, any word on this please?

> > Thanks.
> > 
> >  drivers/pci/msi.c    |    3 +++
> >  drivers/pci/quirks.c |   10 ++++++++++
> >  include/linux/pci.h  |    1 +
> >  3 files changed, 14 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
> > index aca7578..4f36b8b 100644
> > --- a/drivers/pci/msi.c
> > +++ b/drivers/pci/msi.c
> > @@ -1040,6 +1040,9 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
> >  {
> >  	INIT_LIST_HEAD(&dev->msi_list);
> >  
> > +	if (dev->broken_msi_disable)
> > +		return;
> > +
> >  	/* Disable the msi hardware to avoid screaming interrupts
> >  	 * during boot.  This is the power on reset default so
> >  	 * usually this should be a noop.
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index e85d230..4ba3400 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -2890,6 +2890,16 @@ static void quirk_intel_ntb(struct pci_dev *dev)
> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
> >  
> > +/*
> > + * 3ware 9650SE controller doesn't properly initialize if MSI are
> > + * disabled on it during PCI device discovery
> > + */
> > +static void quirk_broken_msi_disable(struct pci_dev *dev)
> > +{
> > +	dev->broken_msi_disable = 1;
> > +}
> > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_3WARE, 0x1004, quirk_broken_msi_disable);
> > +
> >  static ktime_t fixup_debug_start(struct pci_dev *dev,
> >  				 void (*fn)(struct pci_dev *dev))
> >  {
> > diff --git a/include/linux/pci.h b/include/linux/pci.h
> > index 0fd1f15..c327d74 100644
> > --- a/include/linux/pci.h
> > +++ b/include/linux/pci.h
> > @@ -341,6 +341,7 @@ struct pci_dev {
> >  #ifdef CONFIG_PCI_MSI
> >  	struct list_head msi_list;
> >  	struct kset *msi_kset;
> > +	unsigned int	broken_msi_disable:1;
> >  #endif
> >  	struct pci_vpd *vpd;
> >  #ifdef CONFIG_PCI_ATS
> > 
> > -- 
> > Jiri Kosina
> > SUSE Labs
> > 
> 
> -- 
> Jiri Kosina
> SUSE Labs
> 

-- 
Jiri Kosina
SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-08-28 15:46   ` Jiri Kosina
@ 2013-08-28 16:33     ` Bjorn Helgaas
  2013-09-06  9:51       ` Jiri Kosina
  0 siblings, 1 reply; 14+ messages in thread
From: Bjorn Helgaas @ 2013-08-28 16:33 UTC (permalink / raw)
  To: Jiri Kosina
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

[+cc another email addr for Adam from git logs]

On Wed, Aug 28, 2013 at 9:46 AM, Jiri Kosina <jkosina@suse.cz> wrote:
> On Tue, 27 Aug 2013, Jiri Kosina wrote:
>
>> On Tue, 27 Aug 2013, Jiri Kosina wrote:
>>
>> > Commit d5dea7d95 ("PCI: msi: Disable msi interrupts when we initialize a
>> > pci device") makes MSIs be forcibly disabled at boot time.
>> >
>> > It turns out that this breaks 3ware controller -- if MSIs are disabled
>> > during PCI discovery of this controller, the device doesn't work properly
>> > (it doesn't respond to any commands that are being sent to it after
>> > initialization).
>> >
>> > Reverting d5dea7d95 or not force-disabling MSIs in pci_msi_init_pci_dev()
>> > makes the device work properly again.
>> >
>> > Signed-off-by: Jiri Kosina <jkosina@suse.cz>
>> >
>> > ---
>> >
>> > I am adding Adam Radford as a recepient as well, to see whether he is able
>> > to provide some more explanation why this device would expose this
>> > behavior.
>
> OK, so Adam Radford's lsi.com address is bouncing, hence I guess we can't
> expect any feedback from him.
>
> Bjorn, Jesse, any word on this please?

It's on my list to look at.  It's too late to put it in for v3.11, and
it's doubtful that it will even make the v3.12 merge window (though
possibly it could go in post-merge window).  d5dea7d95 is several
years old, so hopefully this issue isn't super-urgent.  Let me know if
otherwise.

Bjorn

>> >  drivers/pci/msi.c    |    3 +++
>> >  drivers/pci/quirks.c |   10 ++++++++++
>> >  include/linux/pci.h  |    1 +
>> >  3 files changed, 14 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
>> > index aca7578..4f36b8b 100644
>> > --- a/drivers/pci/msi.c
>> > +++ b/drivers/pci/msi.c
>> > @@ -1040,6 +1040,9 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
>> >  {
>> >     INIT_LIST_HEAD(&dev->msi_list);
>> >
>> > +   if (dev->broken_msi_disable)
>> > +           return;
>> > +
>> >     /* Disable the msi hardware to avoid screaming interrupts
>> >      * during boot.  This is the power on reset default so
>> >      * usually this should be a noop.
>> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
>> > index e85d230..4ba3400 100644
>> > --- a/drivers/pci/quirks.c
>> > +++ b/drivers/pci/quirks.c
>> > @@ -2890,6 +2890,16 @@ static void quirk_intel_ntb(struct pci_dev *dev)
>> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
>> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
>> >
>> > +/*
>> > + * 3ware 9650SE controller doesn't properly initialize if MSI are
>> > + * disabled on it during PCI device discovery
>> > + */
>> > +static void quirk_broken_msi_disable(struct pci_dev *dev)
>> > +{
>> > +   dev->broken_msi_disable = 1;
>> > +}
>> > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_3WARE, 0x1004, quirk_broken_msi_disable);
>> > +
>> >  static ktime_t fixup_debug_start(struct pci_dev *dev,
>> >                              void (*fn)(struct pci_dev *dev))
>> >  {
>> > diff --git a/include/linux/pci.h b/include/linux/pci.h
>> > index 0fd1f15..c327d74 100644
>> > --- a/include/linux/pci.h
>> > +++ b/include/linux/pci.h
>> > @@ -341,6 +341,7 @@ struct pci_dev {
>> >  #ifdef CONFIG_PCI_MSI
>> >     struct list_head msi_list;
>> >     struct kset *msi_kset;
>> > +   unsigned int    broken_msi_disable:1;
>> >  #endif
>> >     struct pci_vpd *vpd;
>> >  #ifdef CONFIG_PCI_ATS
>> >
>> > --
>> > Jiri Kosina
>> > SUSE Labs
>> >
>>
>> --
>> Jiri Kosina
>> SUSE Labs
>>
>
> --
> Jiri Kosina
> SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-08-28 16:33     ` Bjorn Helgaas
@ 2013-09-06  9:51       ` Jiri Kosina
  2013-09-06 22:47         ` Bjorn Helgaas
  0 siblings, 1 reply; 14+ messages in thread
From: Jiri Kosina @ 2013-09-06  9:51 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

On Wed, 28 Aug 2013, Bjorn Helgaas wrote:

> [+cc another email addr for Adam from git logs]

Thanks. Adam, would you happen to have any possible explanation / 
background?

> >> > Commit d5dea7d95 ("PCI: msi: Disable msi interrupts when we initialize a
> >> > pci device") makes MSIs be forcibly disabled at boot time.
> >> >
> >> > It turns out that this breaks 3ware controller -- if MSIs are disabled
> >> > during PCI discovery of this controller, the device doesn't work properly
> >> > (it doesn't respond to any commands that are being sent to it after
> >> > initialization).
> >> >
> >> > Reverting d5dea7d95 or not force-disabling MSIs in pci_msi_init_pci_dev()
> >> > makes the device work properly again.
> >> >
> >> > Signed-off-by: Jiri Kosina <jkosina@suse.cz>
> >> >
> >> > ---
> >> >
> >> > I am adding Adam Radford as a recepient as well, to see whether he is able
> >> > to provide some more explanation why this device would expose this
> >> > behavior.
> >
> > OK, so Adam Radford's lsi.com address is bouncing, hence I guess we can't
> > expect any feedback from him.
> >
> > Bjorn, Jesse, any word on this please?
> 
> It's on my list to look at.  It's too late to put it in for v3.11, and
> it's doubtful that it will even make the v3.12 merge window (though
> possibly it could go in post-merge window).  d5dea7d95 is several
> years old, so hopefully this issue isn't super-urgent.  Let me know if
> otherwise.

I agree that this should be applicable to 3.12-rcX as well, as it's very 
device-specific.

Thanks.

> 
> Bjorn
> 
> >> >  drivers/pci/msi.c    |    3 +++
> >> >  drivers/pci/quirks.c |   10 ++++++++++
> >> >  include/linux/pci.h  |    1 +
> >> >  3 files changed, 14 insertions(+), 0 deletions(-)
> >> >
> >> > diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
> >> > index aca7578..4f36b8b 100644
> >> > --- a/drivers/pci/msi.c
> >> > +++ b/drivers/pci/msi.c
> >> > @@ -1040,6 +1040,9 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
> >> >  {
> >> >     INIT_LIST_HEAD(&dev->msi_list);
> >> >
> >> > +   if (dev->broken_msi_disable)
> >> > +           return;
> >> > +
> >> >     /* Disable the msi hardware to avoid screaming interrupts
> >> >      * during boot.  This is the power on reset default so
> >> >      * usually this should be a noop.
> >> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> >> > index e85d230..4ba3400 100644
> >> > --- a/drivers/pci/quirks.c
> >> > +++ b/drivers/pci/quirks.c
> >> > @@ -2890,6 +2890,16 @@ static void quirk_intel_ntb(struct pci_dev *dev)
> >> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
> >> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
> >> >
> >> > +/*
> >> > + * 3ware 9650SE controller doesn't properly initialize if MSI are
> >> > + * disabled on it during PCI device discovery
> >> > + */
> >> > +static void quirk_broken_msi_disable(struct pci_dev *dev)
> >> > +{
> >> > +   dev->broken_msi_disable = 1;
> >> > +}
> >> > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_3WARE, 0x1004, quirk_broken_msi_disable);
> >> > +
> >> >  static ktime_t fixup_debug_start(struct pci_dev *dev,
> >> >                              void (*fn)(struct pci_dev *dev))
> >> >  {
> >> > diff --git a/include/linux/pci.h b/include/linux/pci.h
> >> > index 0fd1f15..c327d74 100644
> >> > --- a/include/linux/pci.h
> >> > +++ b/include/linux/pci.h
> >> > @@ -341,6 +341,7 @@ struct pci_dev {
> >> >  #ifdef CONFIG_PCI_MSI
> >> >     struct list_head msi_list;
> >> >     struct kset *msi_kset;
> >> > +   unsigned int    broken_msi_disable:1;
> >> >  #endif
> >> >     struct pci_vpd *vpd;
> >> >  #ifdef CONFIG_PCI_ATS
> >> >
> >> > --
> >> > Jiri Kosina
> >> > SUSE Labs
> >> >
> >>
> >> --
> >> Jiri Kosina
> >> SUSE Labs
> >>
> >
> > --
> > Jiri Kosina
> > SUSE Labs
> 

-- 
Jiri Kosina
SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-09-06  9:51       ` Jiri Kosina
@ 2013-09-06 22:47         ` Bjorn Helgaas
  2013-09-24 20:50           ` Bjorn Helgaas
  2013-09-27  9:08           ` Jiri Kosina
  0 siblings, 2 replies; 14+ messages in thread
From: Bjorn Helgaas @ 2013-09-06 22:47 UTC (permalink / raw)
  To: Jiri Kosina
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

On Fri, Sep 6, 2013 at 3:51 AM, Jiri Kosina <jkosina@suse.cz> wrote:
> On Wed, 28 Aug 2013, Bjorn Helgaas wrote:
>
>> [+cc another email addr for Adam from git logs]
>
> Thanks. Adam, would you happen to have any possible explanation /
> background?
>
>> >> > Commit d5dea7d95 ("PCI: msi: Disable msi interrupts when we initialize a
>> >> > pci device") makes MSIs be forcibly disabled at boot time.
>> >> >
>> >> > It turns out that this breaks 3ware controller -- if MSIs are disabled
>> >> > during PCI discovery of this controller, the device doesn't work properly
>> >> > (it doesn't respond to any commands that are being sent to it after
>> >> > initialization).

Is there a bug report for this issue?  It's nice to have a pointer to,
e.g., a bugzilla.kernel.org bug report with info such as dmesg logs,
lspci output, etc., for future reference.  Maybe somebody will figure
out a more generic change that could make this quirk unnecessary, and
details will help in figuring that out.

I assume the actual PCI discovery done in the PCI core works fine;
it's just that the driver doesn't work if MSIs are disabled on the
device.  If that's the case, can this be fixed by some driver change?
Maybe the driver needs to enable MSI before it sends commands to the
device?

Any description of what this failure looks like to a user?  How can a
user or a distro connect a symptom (driver timeout, console message,
or whatever) to this patch?

>> >> > Reverting d5dea7d95 or not force-disabling MSIs in pci_msi_init_pci_dev()
>> >> > makes the device work properly again.
>> >> >
>> >> > Signed-off-by: Jiri Kosina <jkosina@suse.cz>
>> >> >
>> >> > ---
>> >> >
>> >> > I am adding Adam Radford as a recepient as well, to see whether he is able
>> >> > to provide some more explanation why this device would expose this
>> >> > behavior.
>> >
>> > OK, so Adam Radford's lsi.com address is bouncing, hence I guess we can't
>> > expect any feedback from him.
>> >
>> > Bjorn, Jesse, any word on this please?
>>
>> It's on my list to look at.  It's too late to put it in for v3.11, and
>> it's doubtful that it will even make the v3.12 merge window (though
>> possibly it could go in post-merge window).  d5dea7d95 is several
>> years old, so hopefully this issue isn't super-urgent.  Let me know if
>> otherwise.
>
> I agree that this should be applicable to 3.12-rcX as well, as it's very
> device-specific.
>
> Thanks.
>
>>
>> Bjorn
>>
>> >> >  drivers/pci/msi.c    |    3 +++
>> >> >  drivers/pci/quirks.c |   10 ++++++++++
>> >> >  include/linux/pci.h  |    1 +
>> >> >  3 files changed, 14 insertions(+), 0 deletions(-)
>> >> >
>> >> > diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
>> >> > index aca7578..4f36b8b 100644
>> >> > --- a/drivers/pci/msi.c
>> >> > +++ b/drivers/pci/msi.c
>> >> > @@ -1040,6 +1040,9 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
>> >> >  {
>> >> >     INIT_LIST_HEAD(&dev->msi_list);
>> >> >
>> >> > +   if (dev->broken_msi_disable)
>> >> > +           return;
>> >> > +
>> >> >     /* Disable the msi hardware to avoid screaming interrupts
>> >> >      * during boot.  This is the power on reset default so
>> >> >      * usually this should be a noop.
>> >> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
>> >> > index e85d230..4ba3400 100644
>> >> > --- a/drivers/pci/quirks.c
>> >> > +++ b/drivers/pci/quirks.c
>> >> > @@ -2890,6 +2890,16 @@ static void quirk_intel_ntb(struct pci_dev *dev)
>> >> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
>> >> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
>> >> >
>> >> > +/*
>> >> > + * 3ware 9650SE controller doesn't properly initialize if MSI are
>> >> > + * disabled on it during PCI device discovery
>> >> > + */
>> >> > +static void quirk_broken_msi_disable(struct pci_dev *dev)
>> >> > +{
>> >> > +   dev->broken_msi_disable = 1;
>> >> > +}
>> >> > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_3WARE, 0x1004, quirk_broken_msi_disable);
>> >> > +
>> >> >  static ktime_t fixup_debug_start(struct pci_dev *dev,
>> >> >                              void (*fn)(struct pci_dev *dev))
>> >> >  {
>> >> > diff --git a/include/linux/pci.h b/include/linux/pci.h
>> >> > index 0fd1f15..c327d74 100644
>> >> > --- a/include/linux/pci.h
>> >> > +++ b/include/linux/pci.h
>> >> > @@ -341,6 +341,7 @@ struct pci_dev {
>> >> >  #ifdef CONFIG_PCI_MSI
>> >> >     struct list_head msi_list;
>> >> >     struct kset *msi_kset;
>> >> > +   unsigned int    broken_msi_disable:1;
>> >> >  #endif
>> >> >     struct pci_vpd *vpd;
>> >> >  #ifdef CONFIG_PCI_ATS
>> >> >
>> >> > --
>> >> > Jiri Kosina
>> >> > SUSE Labs
>> >> >
>> >>
>> >> --
>> >> Jiri Kosina
>> >> SUSE Labs
>> >>
>> >
>> > --
>> > Jiri Kosina
>> > SUSE Labs
>>
>
> --
> Jiri Kosina
> SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-09-06 22:47         ` Bjorn Helgaas
@ 2013-09-24 20:50           ` Bjorn Helgaas
  2013-09-27  9:08           ` Jiri Kosina
  1 sibling, 0 replies; 14+ messages in thread
From: Bjorn Helgaas @ 2013-09-24 20:50 UTC (permalink / raw)
  To: Jiri Kosina
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

On Fri, Sep 6, 2013 at 4:47 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> On Fri, Sep 6, 2013 at 3:51 AM, Jiri Kosina <jkosina@suse.cz> wrote:

>>> >> > Commit d5dea7d95 ("PCI: msi: Disable msi interrupts when we initialize a
>>> >> > pci device") makes MSIs be forcibly disabled at boot time.
>>> >> >
>>> >> > It turns out that this breaks 3ware controller -- if MSIs are disabled
>>> >> > during PCI discovery of this controller, the device doesn't work properly
>>> >> > (it doesn't respond to any commands that are being sent to it after
>>> >> > initialization).
>
> Is there a bug report for this issue?  It's nice to have a pointer to,
> e.g., a bugzilla.kernel.org bug report with info such as dmesg logs,
> lspci output, etc., for future reference.  Maybe somebody will figure
> out a more generic change that could make this quirk unnecessary, and
> details will help in figuring that out.
>
> I assume the actual PCI discovery done in the PCI core works fine;
> it's just that the driver doesn't work if MSIs are disabled on the
> device.  If that's the case, can this be fixed by some driver change?
> Maybe the driver needs to enable MSI before it sends commands to the
> device?

Ping?  Since the complaint is that the device doesn't work unless MSIs
are enabled, can this be fixed in the driver instead of in a quirk?

> Any description of what this failure looks like to a user?  How can a
> user or a distro connect a symptom (driver timeout, console message,
> or whatever) to this patch?
>
>>> >> > Reverting d5dea7d95 or not force-disabling MSIs in pci_msi_init_pci_dev()
>>> >> > makes the device work properly again.
>>> >> >
>>> >> > Signed-off-by: Jiri Kosina <jkosina@suse.cz>
>>> >> >
>>> >> > ---
>>> >> >
>>> >> > I am adding Adam Radford as a recepient as well, to see whether he is able
>>> >> > to provide some more explanation why this device would expose this
>>> >> > behavior.
>>> >
>>> > OK, so Adam Radford's lsi.com address is bouncing, hence I guess we can't
>>> > expect any feedback from him.
>>> >
>>> > Bjorn, Jesse, any word on this please?
>>>
>>> It's on my list to look at.  It's too late to put it in for v3.11, and
>>> it's doubtful that it will even make the v3.12 merge window (though
>>> possibly it could go in post-merge window).  d5dea7d95 is several
>>> years old, so hopefully this issue isn't super-urgent.  Let me know if
>>> otherwise.
>>
>> I agree that this should be applicable to 3.12-rcX as well, as it's very
>> device-specific.
>>
>> Thanks.
>>
>>>
>>> Bjorn
>>>
>>> >> >  drivers/pci/msi.c    |    3 +++
>>> >> >  drivers/pci/quirks.c |   10 ++++++++++
>>> >> >  include/linux/pci.h  |    1 +
>>> >> >  3 files changed, 14 insertions(+), 0 deletions(-)
>>> >> >
>>> >> > diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
>>> >> > index aca7578..4f36b8b 100644
>>> >> > --- a/drivers/pci/msi.c
>>> >> > +++ b/drivers/pci/msi.c
>>> >> > @@ -1040,6 +1040,9 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
>>> >> >  {
>>> >> >     INIT_LIST_HEAD(&dev->msi_list);
>>> >> >
>>> >> > +   if (dev->broken_msi_disable)
>>> >> > +           return;
>>> >> > +
>>> >> >     /* Disable the msi hardware to avoid screaming interrupts
>>> >> >      * during boot.  This is the power on reset default so
>>> >> >      * usually this should be a noop.
>>> >> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
>>> >> > index e85d230..4ba3400 100644
>>> >> > --- a/drivers/pci/quirks.c
>>> >> > +++ b/drivers/pci/quirks.c
>>> >> > @@ -2890,6 +2890,16 @@ static void quirk_intel_ntb(struct pci_dev *dev)
>>> >> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
>>> >> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
>>> >> >
>>> >> > +/*
>>> >> > + * 3ware 9650SE controller doesn't properly initialize if MSI are
>>> >> > + * disabled on it during PCI device discovery
>>> >> > + */
>>> >> > +static void quirk_broken_msi_disable(struct pci_dev *dev)
>>> >> > +{
>>> >> > +   dev->broken_msi_disable = 1;
>>> >> > +}
>>> >> > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_3WARE, 0x1004, quirk_broken_msi_disable);
>>> >> > +
>>> >> >  static ktime_t fixup_debug_start(struct pci_dev *dev,
>>> >> >                              void (*fn)(struct pci_dev *dev))
>>> >> >  {
>>> >> > diff --git a/include/linux/pci.h b/include/linux/pci.h
>>> >> > index 0fd1f15..c327d74 100644
>>> >> > --- a/include/linux/pci.h
>>> >> > +++ b/include/linux/pci.h
>>> >> > @@ -341,6 +341,7 @@ struct pci_dev {
>>> >> >  #ifdef CONFIG_PCI_MSI
>>> >> >     struct list_head msi_list;
>>> >> >     struct kset *msi_kset;
>>> >> > +   unsigned int    broken_msi_disable:1;
>>> >> >  #endif
>>> >> >     struct pci_vpd *vpd;
>>> >> >  #ifdef CONFIG_PCI_ATS
>>> >> >
>>> >> > --
>>> >> > Jiri Kosina
>>> >> > SUSE Labs
>>> >> >
>>> >>
>>> >> --
>>> >> Jiri Kosina
>>> >> SUSE Labs
>>> >>
>>> >
>>> > --
>>> > Jiri Kosina
>>> > SUSE Labs
>>>
>>
>> --
>> Jiri Kosina
>> SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-09-06 22:47         ` Bjorn Helgaas
  2013-09-24 20:50           ` Bjorn Helgaas
@ 2013-09-27  9:08           ` Jiri Kosina
  2013-10-30 10:27             ` Jiri Kosina
  1 sibling, 1 reply; 14+ messages in thread
From: Jiri Kosina @ 2013-09-27  9:08 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

On Fri, 6 Sep 2013, Bjorn Helgaas wrote:

> >> >> > Commit d5dea7d95 ("PCI: msi: Disable msi interrupts when we initialize a
> >> >> > pci device") makes MSIs be forcibly disabled at boot time.
> >> >> >
> >> >> > It turns out that this breaks 3ware controller -- if MSIs are disabled
> >> >> > during PCI discovery of this controller, the device doesn't work properly
> >> >> > (it doesn't respond to any commands that are being sent to it after
> >> >> > initialization).
> 
> Is there a bug report for this issue?  

Yes, but unfortunately only in our internal bugzilla.

> It's nice to have a pointer to, e.g., a bugzilla.kernel.org bug report 
> with info such as dmesg logs, lspci output, etc., for future reference.  

It's a customer-reported issue, so I am gathering permission to make this 
information public (I don't think that'll be an issue).

I'll send up a followup afterwards.

> Maybe somebody will figure out a more generic change that could make 
> this quirk unnecessary, and details will help in figuring that out.
> 
> I assume the actual PCI discovery done in the PCI core works fine;
> it's just that the driver doesn't work if MSIs are disabled on the
> device.  If that's the case, can this be fixed by some driver change?
> Maybe the driver needs to enable MSI before it sends commands to the
> device?

I have tried it, but it still doesn't work. It seems like the device 
initialization is not finalized properly with MISs disabled; meaning the 
device is there (discovery has completed), but it "just doesn't work".

> Any description of what this failure looks like to a user?  How can a 
> user or a distro connect a symptom (driver timeout, console message, or 
> whatever) to this patch?

Will be hopefully part of the dmesg I will be providing later ... 
basically any commands sent to it time out.

Thanks,

-- 
Jiri Kosina
SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-09-27  9:08           ` Jiri Kosina
@ 2013-10-30 10:27             ` Jiri Kosina
  2013-10-31 21:27               ` Bjorn Helgaas
  0 siblings, 1 reply; 14+ messages in thread
From: Jiri Kosina @ 2013-10-30 10:27 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

[-- Attachment #1: Type: TEXT/PLAIN, Size: 642 bytes --]

On Fri, 27 Sep 2013, Jiri Kosina wrote:

> > It's nice to have a pointer to, e.g., a bugzilla.kernel.org bug report 
> > with info such as dmesg logs, lspci output, etc., for future reference.  
> 
> It's a customer-reported issue, so I am gathering permission to make this 
> information public (I don't think that'll be an issue).
> 
> I'll send up a followup afterwards.

Attached is dmesg output leading to timeouts (that are cured by my 
original patch in this thread) and lspci.

Please let me know if there is anything else I could do, or if you are 
going to proceed with my patch adding the quirk.

Thanks,

-- 
Jiri Kosina
SUSE Labs

[-- Attachment #2: Type: TEXT/plain, Size: 32100 bytes --]

[    0.000000] Initializing cgroup subsys cpuset\r
[    0.000000] Initializing cgroup subsys cpu\r
[    0.000000] Linux version 3.0.58-0.6.6-default (geeko@buildhost) (gcc version 4.3.4 [gcc-4_3-branch revision 152973] (SUSE Linux) ) #1 SMP Tue Feb 19 11:07:00 UTC 2013 (1576ecd)\r
[    0.000000] Command line: root=/dev/disk/by-id/scsi-3600050e0fc071e00f8ea000069410000-part1 resume=/dev/disk/by-id/scsi-3600050e0fc071e00f8ea000069410000-part5 splash=silent crashkernel=256M-:128M showopts console=tty0 console=ttyS0,115200 vga=0x314 scsi_mod.scsi_logging_level=9411\r
[    0.000000] BIOS-provided physical RAM map:\r
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009c800 (usable)\r
[    0.000000]  BIOS-e820: 000000000009c800 - 0000000000100000 (reserved)\r
[    0.000000]  BIOS-e820: 0000000000100000 - 000000009f91a000 (usable)\r
[    0.000000]  BIOS-e820: 000000009f91a000 - 000000009f9d1000 (ACPI NVS)\r
[    0.000000]  BIOS-e820: 000000009f9d1000 - 000000009fa32000 (usable)\r
[    0.000000]  BIOS-e820: 000000009fa32000 - 000000009fa9a000 (reserved)\r
[    0.000000]  BIOS-e820: 000000009fa9a000 - 000000009fab4000 (usable)\r
[    0.000000]  BIOS-e820: 000000009fab4000 - 000000009fb1a000 (ACPI NVS)\r
[    0.000000]  BIOS-e820: 000000009fb1a000 - 000000009fb26000 (usable)\r
[    0.000000]  BIOS-e820: 000000009fb26000 - 000000009fb3a000 (ACPI data)\r
[    0.000000]  BIOS-e820: 000000009fb3a000 - 000000009fc00000 (usable)\r
[    0.000000]  BIOS-e820: 000000009fc00000 - 00000000b0000000 (reserved)\r
[    0.000000]  BIOS-e820: 00000000ffe00000 - 00000000ffe0c000 (reserved)\r
[    0.000000]  BIOS-e820: 0000000100000000 - 0000000460000000 (usable)\r
[    0.000000] NX (Execute Disable) protection: active\r
[    0.000000] DMI 2.5 present.\r
[    0.000000] No AGP bridge found\r
[    0.000000] last_pfn = 0x460000 max_arch_pfn = 0x400000000\r
[    0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106\r
[    0.000000] last_pfn = 0x9fc00 max_arch_pfn = 0x400000000\r
[    0.000000] found SMP MP-table at [ffff8800000fdc80] fdc80\r
[    0.000000] init_memory_mapping: 0000000000000000-000000009fc00000\r
[    0.000000] init_memory_mapping: 0000000100000000-0000000460000000\r
[    0.000000] RAMDISK: 378e4000 - 37ff0000\r
[    0.000000] Reserving 128MB of memory at 752MB for crashkernel (System RAM: 17920MB)\r
[    0.000000] ACPI: RSDP 00000000000f0410 00024 (v02 INTEL )\r
[    0.000000] ACPI: XSDT 000000009fb39120 00084 (v01 INTEL  S5000PSL 00000000 INTL 01000013)\r
[    0.000000] ACPI: FACP 000000009fb37000 000F4 (v03 INTEL  S5000PSL 00000000 INTL 01000013)\r
[    0.000000] ACPI: DSDT 000000009fb30000 05809 (v02 INTEL  S5000PSL 00000001 INTL 01000013)\r
[    0.000000] ACPI: FACS 000000009fab4000 00040\r
[    0.000000] ACPI: APIC 000000009fb36000 000C8 (v01 INTEL  S5000PSL 00000000 INTL 01000013)\r
[    0.000000] ACPI: SPCR 000000009fb2f000 00050 (v01 INTEL  S5000PSL 00000000 INTL 01000013)\r
[    0.000000] ACPI: HPET 000000009fb2e000 00038 (v01 INTEL  S5000PSL 00000001 INTL 01000013)\r
[    0.000000] ACPI: MCFG 000000009fb2d000 0003C (v01 INTEL  S5000PSL 00000001 INTL 01000013)\r
[    0.000000] ACPI: SSDT 000000009fb2c000 00A14 (v02  INTEL EIST     00004000 INTL 20060317)\r
[    0.000000] ACPI: SSDT 000000009fb2b000 00193 (v02  INTEL IPMI     00004000 INTL 20060317)\r
[    0.000000] ACPI: SSDT 000000009fb2a000 002D4 (v02  INTEL CST      00004000 INTL 20060317)\r
[    0.000000] ACPI: HEST 000000009fb29000 000A8 (v01 INTEL  S5000PSL 00000001 INTL 00000001)\r
[    0.000000] ACPI: BERT 000000009fb28000 00030 (v01 INTEL  S5000PSL 00000001 INTL 00000001)\r
[    0.000000] ACPI: ERST 000000009fb27000 00230 (v01 INTEL  S5000PSL 00000001 INTL 00000001)\r
[    0.000000] ACPI: EINJ 000000009fb26000 00130 (v01 INTEL  S5000PSL 00000001 INTL 00000001)\r
[    0.000000] No NUMA configuration found\r
[    0.000000] Faking a node at 0000000000000000-0000000460000000\r
[    0.000000] Initmem setup node 0 0000000000000000-0000000460000000\r
[    0.000000]   NODE_DATA [000000045ffd9000 - 000000045fffffff]\r
[    0.000000] Zone PFN ranges:\r
[    0.000000]   DMA      0x00000010 -> 0x00001000\r
[    0.000000]   DMA32    0x00001000 -> 0x00100000\r
[    0.000000]   Normal   0x00100000 -> 0x00460000\r
[    0.000000] Movable zone start PFN for each node\r
[    0.000000] early_node_map[7] active PFN ranges\r
[    0.000000]     0: 0x00000010 -> 0x0000009c\r
[    0.000000]     0: 0x00000100 -> 0x0009f91a\r
[    0.000000]     0: 0x0009f9d1 -> 0x0009fa32\r
[    0.000000]     0: 0x0009fa9a -> 0x0009fab4\r
[    0.000000]     0: 0x0009fb1a -> 0x0009fb26\r
[    0.000000]     0: 0x0009fb3a -> 0x0009fc00\r
[    0.000000]     0: 0x00100000 -> 0x00460000\r
[    0.000000] ACPI: PM-Timer IO Port: 0x408\r
[    0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)\r
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x02] enabled)\r
[    0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x04] enabled)\r
[    0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x06] enabled)\r
[    0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x01] enabled)\r
[    0.000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0x03] enabled)\r
[    0.000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0x05] enabled)\r
[    0.000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0x07] enabled)\r
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high level lint[0x1])\r
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1])\r
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1])\r
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1])\r
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1])\r
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x05] high level lint[0x1])\r
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x06] high level lint[0x1])\r
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x07] high level lint[0x1])\r
[    0.000000] ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])\r
[    0.000000] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23\r
[    0.000000] ACPI: IOAPIC (id[0x09] address[0xfec80000] gsi_base[24])\r
[    0.000000] IOAPIC[1]: apic_id 9, version 32, address 0xfec80000, GSI 24-47\r
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)\r
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)\r
[    0.000000] Using ACPI (MADT) for SMP configuration information\r
[    0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000\r
[    0.000000] SMP: Allowing 8 CPUs, 0 hotplug CPUs\r
[    0.000000] PM: Registered nosave memory: 000000000009c000 - 000000000009d000\r
[    0.000000] PM: Registered nosave memory: 000000000009d000 - 0000000000100000\r
[    0.000000] PM: Registered nosave memory: 000000009f91a000 - 000000009f9d1000\r
[    0.000000] PM: Registered nosave memory: 000000009fa32000 - 000000009fa9a000\r
[    0.000000] PM: Registered nosave memory: 000000009fab4000 - 000000009fb1a000\r
[    0.000000] PM: Registered nosave memory: 000000009fb26000 - 000000009fb3a000\r
[    0.000000] PM: Registered nosave memory: 000000009fc00000 - 00000000b0000000\r
[    0.000000] PM: Registered nosave memory: 00000000b0000000 - 00000000ffe00000\r
[    0.000000] PM: Registered nosave memory: 00000000ffe00000 - 00000000ffe0c000\r
[    0.000000] PM: Registered nosave memory: 00000000ffe0c000 - 0000000100000000\r
[    0.000000] Allocating PCI resources starting at b0000000 (gap: b0000000:4fe00000)\r
[    0.000000] Booting paravirtualized kernel on bare hardware\r
[    0.000000] setup_percpu: NR_CPUS:4096 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1\r
[    0.000000] PERCPU: Embedded 25 pages/cpu @ffff88045fc00000 s73728 r8192 d20480 u262144\r
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 4130030\r
[    0.000000] Policy zone: Normal\r
[    0.000000] Kernel command line: root=/dev/disk/by-id/scsi-3600050e0fc071e00f8ea000069410000-part1 resume=/dev/disk/by-id/scsi-3600050e0fc071e00f8ea000069410000-part5 splash=silent crashkernel=256M-:128M showopts console=tty0 console=ttyS0,115200 vga=0x314 scsi_mod.scsi_logging_level=9411\r
[    0.000000] bootsplash: silent mode.\r
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)\r
[    0.000000] Checking aperture...\r
[    0.000000] No AGP bridge found\r
[    0.000000] Memory: 16317736k/18350080k available (4419k kernel code, 1579060k absent, 453284k reserved, 7676k data, 1344k init)\r
[    0.000000] Hierarchical RCU implementation.\r
[    0.000000]  RCU dyntick-idle grace-period acceleration is enabled.\r
[    0.000000] NR_IRQS:262400 nr_irqs:1152 16\r
[    0.000000] Extended CMOS year: 2000\r
[    0.000000] Console: colour dummy device 80x25\r
[    0.000000] console [tty0] enabled\r
[    0.000000] console [ttyS0] enabled\r
[    0.000000] allocated 134217728 bytes of page_cgroup\r
[    0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups\r
[    0.000000] Fast TSC calibration using PIT\r
[    0.000000] Detected 2327.672 MHz processor.\r
[    0.008005] Calibrating delay loop (skipped), value calculated using timer frequency.. 4655.34 BogoMIPS (lpj=9310688)\r
[    0.014789] pid_max: default: 32768 minimum: 301\r
[    0.016511] kdb version 4.4 by Keith Owens, Scott Lurndal. Copyright SGI, All Rights Reserved\r
kdb_cmd[0]: defcmd archkdb "" "First line arch debugging"\r
kdb_cmd[8]: defcmd archkdbcpu "" "archkdb with only tasks on cpus"\r
kdb_cmd[15]: defcmd archkdbshort "" "archkdb with less detailed backtrace"\r
kdb_cmd[22]: defcmd archkdbcommon "" "Common arch debugging"\r
[    0.036309] Security Framework initialized\r
[    0.040030] AppArmor: AppArmor initialized\r
[    0.045409] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)\r
[    0.058181] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)\r
[    0.065493] Mount-cache hash table entries: 256\r
[    0.068247] Initializing cgroup subsys cpuacct\r
[    0.072011] Initializing cgroup subsys memory\r
[    0.076033] Initializing cgroup subsys devices\r
[    0.080008] Initializing cgroup subsys freezer\r
[    0.084007] Initializing cgroup subsys net_cls\r
[    0.088007] Initializing cgroup subsys blkio\r
[    0.092016] Initializing cgroup subsys perf_event\r
[    0.096092] CPU: Physical Processor ID: 0\r
[    0.100008] CPU: Processor Core ID: 0\r
[    0.104009] mce: CPU supports 6 MCE banks\r
[    0.108015] CPU0: Thermal monitoring enabled (TM2)\r
[    0.112010] using mwait in idle threads.\r
[    0.120666] ACPI: Core revision 20110413\r
[    0.128564] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1\r
[    0.175161] CPU0: Intel(R) Xeon(R) CPU           E5345  @ 2.33GHz stepping 07\r
[    0.184010] Performance Events: PEBS fmt0-, Core2 events, Intel PMU driver.\r
[    0.186907] PEBS disabled due to CPU errata.\r
[    0.188014] ... version:                2\r
[    0.192012] ... bit width:              40\r
[    0.196012] ... generic registers:      2\r
[    0.200013] ... value mask:             000000ffffffffff\r
[    0.204013] ... max period:             000000007fffffff\r
[    0.208013] ... fixed-purpose events:   3\r
[    0.212013] ... event mask:             0000000700000003\r
[    0.216406] NMI watchdog enabled, takes one hw-pmu counter.\r
[    0.220193] Booting Node   0, Processors  #1\r
[    0.240043] NMI watchdog enabled, takes one hw-pmu counter.\r
[    0.244193]  #2\r
[    0.340040] NMI watchdog enabled, takes one hw-pmu counter.\r
[    0.344175]  #3\r
[    0.360040] NMI watchdog enabled, takes one hw-pmu counter.\r
[    0.364187]  #4\r
[    0.380076] NMI watchdog enabled, takes one hw-pmu counter.\r
[    0.384241]  #5\r
[    0.400043] NMI watchdog enabled, takes one hw-pmu counter.\r
[    0.404197]  #6\r
[    0.420045] NMI watchdog enabled, takes one hw-pmu counter.\r
[    0.424174]  #7 Ok.\r
[    0.440046] NMI watchdog enabled, takes one hw-pmu counter.\r
[    0.444056] Brought up 8 CPUs\r
[    0.448031] Total of 8 processors activated (37241.80 BogoMIPS).\r
[    0.460347] devtmpfs: initialized\r
[    0.469738] PM: Registering ACPI NVS region at 9f91a000 (749568 bytes)\r
[    0.472054] PM: Registering ACPI NVS region at 9fab4000 (417792 bytes)\r
[    0.476228] print_constraints: dummy:\r
[    0.480058] Time: 15:53:17  Date: 04/09/13\r
[    0.484230] NET: Registered protocol family 16\r
[    0.488197] ACPI: bus type pci registered\r
[    0.492118] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xa0000000-0xafffffff] (base 0xa0000000)\r
[    0.496033] PCI: MMCONFIG at [mem 0xa0000000-0xafffffff] reserved in E820\r
[    0.555786] PCI: Using configuration type 1 for base access\r
[    0.556923] bio: create slab <bio-0> at 0\r
[    0.565658] ACPI: Executed 1 blocks of module-level executable AML code\r
[    0.568324] ACPI: Actual Package length (6) is larger than NumElements field (2), truncated\r
[    0.572037]\r
[    0.573638] ACPI: Actual Package length (6) is larger than NumElements field (2), truncated\r
[    0.580037]\r
[    0.584149] ACPI: Actual Package length (6) is larger than NumElements field (2), truncated\r
[    0.588038]\r
[    0.589639] ACPI: Actual Package length (6) is larger than NumElements field (2), truncated\r
[    0.596038]\r
[    0.600146] ACPI: Actual Package length (6) is larger than NumElements field (2), truncated\r
[    0.604039]\r
[    0.605640] ACPI: Actual Package length (6) is larger than NumElements field (2), truncated\r
[    0.612039]\r
[    0.616148] ACPI: Actual Package length (6) is larger than NumElements field (2), truncated\r
[    0.620040]\r
[    0.621643] ACPI: Actual Package length (6) is larger than NumElements field (2), truncated\r
[    0.624040]\r
[    0.629582] ACPI Error: Field [CPB3] at 96 exceeds Buffer [NULL] size 64 (bits) (20110413/dsopcode-236)\r
[    0.634311] ACPI Error: Method parse/execution failed [\_SB_._OSC] (Node ffff880446c97ec0), AE_AML_BUFFER_LIMIT (20110413/psparse-536)\r
[    0.646507] ACPI: Interpreter enabled\r
[    0.648043] ACPI: (supports S0 S1 S4 S5)\r
[    0.653172] ACPI: Using IOAPIC for interrupt routing\r
[    0.661795] ACPI: No dock devices found.\r
[    0.664045] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug\r
[    0.673148] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])\r
[    0.683832] pci_root PNP0A03:00: host bridge window [io  0x0000-0x0ca1]\r
[    0.684045] pci_root PNP0A03:00: host bridge window [io  0x0ca4-0x0cf7]\r
[    0.688044] pci_root PNP0A03:00: host bridge window [io  0x0d00-0xffff]\r
[    0.692045] pci_root PNP0A03:00: host bridge window [mem 0x000a0000-0x000bffff]\r
[    0.696045] pci_root PNP0A03:00: host bridge window [mem 0x000c0000-0x000fffff]\r
[    0.700045] pci_root PNP0A03:00: host bridge window [mem 0xb0000000-0xfdffffff]\r
[    0.704045] pci_root PNP0A03:00: host bridge window [mem 0xfe700000-0xfe7003ff]\r
[    0.708046] pci_root PNP0A03:00: host bridge window [mem 0xfed40000-0xfed44fff]\r
[    0.718380] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\r
[    0.720143] pci 0000:00:02.0: PCI bridge to [bus 01-06]\r
[    0.729051] pci 0000:02:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\r
[    0.737510] pci 0000:02:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\r
[    0.744138] pci 0000:01:00.0: PCI bridge to [bus 02-04]\r
[    0.749194] pci 0000:02:00.0: PCI bridge to [bus 03-03]\r
[    0.767619] pci 0000:04:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\r
[    0.768281] pci 0000:02:02.0: PCI bridge to [bus 04-04]\r
[    0.785193] pci 0000:01:00.3: PCI bridge to [bus 05-06]\r
[    0.813745] pci 0000:05:02.0: PCI bridge to [bus 06-06]\r
[    0.816956] pci 0000:00:03.0: PCI bridge to [bus 07-07]\r
[    0.828065] pci 0000:00:04.0: PCI bridge to [bus 08-08]\r
[    0.832090] pci 0000:00:05.0: PCI bridge to [bus 09-09]\r
[    0.836089] pci 0000:00:06.0: PCI bridge to [bus 0a-0a]\r
[    0.840089] pci 0000:00:07.0: PCI bridge to [bus 0b-0b]\r
[    0.844101] pci 0000:00:1c.0: PCI bridge to [bus 0c-0c]\r
[    0.848262] pci 0000:00:1e.0: PCI bridge to [bus 0d-0d] (subtractive decode)\r
[    0.853054]  pci0000:00: Requesting ACPI _OSC control (0x1d)\r
[    0.856057]  pci0000:00: ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d\r
[    0.860054] ACPI _OSC control for PCIe not granted, disabling ASPM\r
[    0.874266] ACPI: PCI Interrupt Link [LNKA] (IRQs 5 7 *10 11)\r
[    0.880122] ACPI: PCI Interrupt Link [LNKB] (IRQs 5 7 10 *11)\r
[    0.885448] ACPI: PCI Interrupt Link [LNKC] (IRQs *5 7 10 11)\r
[    0.889437] ACPI: PCI Interrupt Link [LNKD] (IRQs 5 7 10 *11)\r
[    0.893439] ACPI: PCI Interrupt Link [LNKE] (IRQs 5 7 *10 11)\r
[    0.897439] ACPI: PCI Interrupt Link [LNKF] (IRQs 5 7 10 *11)\r
[    0.901442] ACPI: PCI Interrupt Link [LNKG] (IRQs *5 7 10 11)\r
[    0.905440] ACPI: PCI Interrupt Link [LNKH] (IRQs 5 7 10 *11)\r
[    0.909480] vgaarb: device added: PCI:0000:0d:0c.0,decodes=io+mem,owns=io+mem,locks=none\r
[    0.912059] vgaarb: loaded\r
[    0.916130] PCI: Using ACPI for IRQ routing\r
[    0.927684] NetLabel: Initializing\r
[    0.928059] NetLabel:  domain hash size = 128\r
[    0.932059] NetLabel:  protocols = UNLABELED CIPSOv4\r
[    0.936073] NetLabel:  unlabeled traffic allowed by default\r
[    0.940063] HPET: 3 timers in total, 0 timers will be used for per-cpu timer\r
[    0.944062] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0\r
[    0.948993] hpet0: 3 comparators, 64-bit 14.318180 MHz counter\r
[    0.976092] Switching to clocksource hpet\r
[    0.981202] Switched to NOHz mode on CPU #4\r
[    0.981462] Switched to NOHz mode on CPU #6\r
[    0.981721] Switched to NOHz mode on CPU #1\r
[    0.981941] Switched to NOHz mode on CPU #3\r
[    0.983696] Switched to NOHz mode on CPU #2\r
[    0.983869] Switched to NOHz mode on CPU #5\r
[    0.983909] Switched to NOHz mode on CPU #0\r
[    0.984029] Switched to NOHz mode on CPU #7\r
[    1.014710] AppArmor: AppArmor Filesystem Enabled\r
[    1.019476] pnp: PnP ACPI init\r
[    1.022553] ACPI: bus type pnp registered\r
[    1.029213] system 00:01: [mem 0xa0000000-0xafffffff] has been reserved\r
[    1.035839] system 00:01: [mem 0xfed1c000-0xfed1ffff] has been reserved\r
[    1.042455] system 00:01: [mem 0xffc00000-0xffffffff] could not be reserved\r
[    1.049412] system 00:01: [mem 0xfec00000-0xfecfffff] could not be reserved\r
[    1.056369] system 00:01: [mem 0xfee00000-0xfeefffff] has been reserved\r
[    1.062979] system 00:01: [mem 0xfe600000-0xfe6fffff] has been reserved\r
[    1.069590] system 00:01: [mem 0xfe000000-0xfe01ffff] has been reserved\r
[    1.076199] system 00:01: [mem 0x00000000-0x0009ffff] could not be reserved\r
[    1.083615] system 00:06: [io  0x0500-0x053f] has been reserved\r
[    1.089536] system 00:06: [io  0x0400-0x047f] has been reserved\r
[    1.095461] system 00:06: [io  0x0800-0x087f] has been reserved\r
[    1.101376] system 00:06: [io  0x0ca0-0x0caf] could not be reserved\r
[    1.107640] system 00:06: [io  0x0161] has been reserved\r
[    1.112950] system 00:06: [io  0x0162] has been reserved\r
[    1.119497] pnp: PnP ACPI: found 14 devices\r
[    1.123684] ACPI: ACPI bus type pnp unregistered\r
[    1.134417] pci 0000:08:00.0: no compatible bridge window for [mem 0xfffe0000-0xffffffff pref]\r
[    1.143033] pci 0000:0d:0c.0: no compatible bridge window for [mem 0xfffe0000-0xffffffff pref]\r
[    1.152701] pci 0000:00:1c.0: BAR 14: assigned [mem 0xbaf00000-0xbb0fffff]\r
[    1.159578] pci 0000:00:1c.0: BAR 15: assigned [mem 0xbb100000-0xbb2fffff 64bit pref]\r
[    1.167403] pci 0000:00:1c.0: BAR 13: assigned [io  0x6000-0x6fff]\r
[    1.173587] pci 0000:02:00.0: PCI bridge to [bus 03-03]\r
[    1.178808] pci 0000:02:00.0:   bridge window [io  disabled]\r
[    1.184511] pci 0000:02:00.0:   bridge window [mem disabled]\r
[    1.190175] pci 0000:02:00.0:   bridge window [mem pref disabled]\r
[    1.196357] pci 0000:02:02.0: PCI bridge to [bus 04-04]\r
[    1.201584] pci 0000:02:02.0:   bridge window [io  0x4000-0x4fff]\r
[    1.207720] pci 0000:02:02.0:   bridge window [mem 0xba000000-0xba8fffff]\r
[    1.214513] pci 0000:02:02.0:   bridge window [mem pref disabled]\r
[    1.220648] pci 0000:01:00.0: PCI bridge to [bus 02-04]\r
[    1.225877] pci 0000:01:00.0:   bridge window [io  0x4000-0x4fff]\r
[    1.232015] pci 0000:01:00.0:   bridge window [mem 0xba000000-0xba8fffff]\r
[    1.238805] pci 0000:01:00.0:   bridge window [mem pref disabled]\r
[    1.244943] pci 0000:05:02.0: PCI bridge to [bus 06-06]\r
[    1.250170] pci 0000:05:02.0:   bridge window [io  0x3000-0x3fff]\r
[    1.256354] pci 0000:05:02.0:   bridge window [mem 0xba900000-0xba9fffff]\r
[    1.263185] pci 0000:05:02.0:   bridge window [mem pref disabled]\r
[    1.269419] pci 0000:01:00.3: PCI bridge to [bus 05-06]\r
[    1.274644] pci 0000:01:00.3:   bridge window [io  0x3000-0x3fff]\r
[    1.280781] pci 0000:01:00.3:   bridge window [mem 0xba900000-0xbaafffff]\r
[    1.287570] pci 0000:01:00.3:   bridge window [mem pref disabled]\r
[    1.293714] pci 0000:00:02.0: PCI bridge to [bus 01-06]\r
[    1.298943] pci 0000:00:02.0:   bridge window [io  0x3000-0x4fff]\r
[    1.305034] pci 0000:00:02.0:   bridge window [mem 0xba000000-0xbabfffff]\r
[    1.311817] pci 0000:00:02.0:   bridge window [mem pref disabled]\r
[    1.317908] pci 0000:00:03.0: PCI bridge to [bus 07-07]\r
[    1.323129] pci 0000:00:03.0:   bridge window [io  disabled]\r
[    1.328788] pci 0000:00:03.0:   bridge window [mem disabled]\r
[    1.334443] pci 0000:00:03.0:   bridge window [mem pref disabled]\r
[    1.340537] pci 0000:08:00.0: BAR 6: assigned [mem 0xbad20000-0xbad3ffff pref]\r
[    1.347761] pci 0000:00:04.0: PCI bridge to [bus 08-08]\r
[    1.352984] pci 0000:00:04.0:   bridge window [io  0x2000-0x2fff]\r
[    1.359076] pci 0000:00:04.0:   bridge window [mem 0xbad00000-0xbadfffff]\r
[    1.365866] pci 0000:00:04.0:   bridge window [mem 0xb8000000-0xb9ffffff 64bit pref]\r
[    1.373605] pci 0000:00:05.0: PCI bridge to [bus 09-09]\r
[    1.378835] pci 0000:00:05.0:   bridge window [io  disabled]\r
[    1.384494] pci 0000:00:05.0:   bridge window [mem disabled]\r
[    1.390150] pci 0000:00:05.0:   bridge window [mem pref disabled]\r
[    1.396241] pci 0000:00:06.0: PCI bridge to [bus 0a-0a]\r
[    1.401464] pci 0000:00:06.0:   bridge window [io  disabled]\r
[    1.407122] pci 0000:00:06.0:   bridge window [mem disabled]\r
[    1.412779] pci 0000:00:06.0:   bridge window [mem pref disabled]\r
[    1.418870] pci 0000:00:07.0: PCI bridge to [bus 0b-0b]\r
[    1.424097] pci 0000:00:07.0:   bridge window [io  disabled]\r
[    1.429758] pci 0000:00:07.0:   bridge window [mem disabled]\r
[    1.435416] pci 0000:00:07.0:   bridge window [mem pref disabled]\r
[    1.441510] pci 0000:00:1c.0: PCI bridge to [bus 0c-0c]\r
[    1.446741] pci 0000:00:1c.0:   bridge window [io  0x6000-0x6fff]\r
[    1.452833] pci 0000:00:1c.0:   bridge window [mem 0xbaf00000-0xbb0fffff]\r
[    1.459617] pci 0000:00:1c.0:   bridge window [mem 0xbb100000-0xbb2fffff 64bit pref]\r
[    1.467358] pci 0000:0d:0c.0: BAR 6: assigned [mem 0xbac20000-0xbac3ffff pref]\r
[    1.474579] pci 0000:00:1e.0: PCI bridge to [bus 0d-0d]\r
[    1.479804] pci 0000:00:1e.0:   bridge window [io  0x1000-0x1fff]\r
[    1.485896] pci 0000:00:1e.0:   bridge window [mem 0xbac00000-0xbacfffff]\r
[    1.492687] pci 0000:00:1e.0:   bridge window [mem 0xb0000000-0xb7ffffff 64bit pref]\r
[    1.500452] pci 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16\r
[    1.507207] pci 0000:01:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16\r
[    1.514052] pci 0000:02:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16\r
[    1.520948] pci 0000:02:02.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18\r
[    1.528066] pci 0000:00:03.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16\r
[    1.534771] pci 0000:00:04.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16\r
[    1.541476] pci 0000:00:05.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16\r
[    1.548181] pci 0000:00:06.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16\r
[    1.554888] pci 0000:00:07.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16\r
[    1.561594] pci 0000:00:1c.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16\r
[    1.568724] NET: Registered protocol family 2\r
[    1.573625] IP route cache hash table entries: 524288 (order: 10, 4194304 bytes)\r
[    1.583779] TCP established hash table entries: 524288 (order: 11, 8388608 bytes)\r
[    1.595364] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)\r
[    1.602614] TCP: Hash tables configured (established 524288 bind 65536)\r
[    1.609233] TCP reno registered\r
[    1.612401] UDP hash table entries: 8192 (order: 6, 262144 bytes)\r
[    1.618660] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes)\r
[    1.625739] NET: Registered protocol family 1\r
[    1.630177] pci 0000:00:1d.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23\r
[    1.636895] pci 0000:00:1d.0: PCI INT A disabled\r
[    1.641527] pci 0000:00:1d.1: PCI INT B -> GSI 22 (level, low) -> IRQ 22\r
[    1.648244] pci 0000:00:1d.1: PCI INT B disabled\r
[    1.652872] pci 0000:00:1d.2: PCI INT C -> GSI 23 (level, low) -> IRQ 23\r
[    1.659583] pci 0000:00:1d.2: PCI INT C disabled\r
[    1.664214] pci 0000:00:1d.3: PCI INT D -> GSI 22 (level, low) -> IRQ 22\r
[    1.670924] pci 0000:00:1d.3: PCI INT D disabled\r
[    1.675553] pci 0000:00:1d.7: PCI INT A -> GSI 23 (level, low) -> IRQ 23\r
[    1.682391] pci 0000:00:1d.7: PCI INT A disabled\r
[    1.687011] pci 0000:00:1f.0: rerouting interrupts for [8086:2670]\r
[    1.693775] Unpacking initramfs...\r
[    1.826090] Freeing initrd memory: 7216k freed\r
[    1.834056] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)\r
[    1.840532] Placing 64MB software IO TLB between ffff88009b91a000 - ffff88009f91a000\r
[    1.848304] software IO TLB at phys 0x9b91a000 - 0x9f91a000\r
[    1.855206] audit: initializing netlink socket (disabled)\r
[    1.860659] type=2000 audit(1365522796.860:1): initialized\r
[    1.889271] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
[    1.898869] VFS: Disk quotas dquot_6.5.2\r
[    1.902882] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)\r
[    1.909505] msgmni has been set to 7971\r
[    1.913597] alg: No test for stdrng (krng)\r
[    1.917803] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)\r
[    1.925271] io scheduler noop registered\r
[    1.929207] io scheduler deadline registered\r
[    1.933590] io scheduler cfq registered (default)\r
[    1.941066] vesafb: mode is 800x600x16, linelength=1600, pages=16\r
[    1.947175] vesafb: scrolling: redraw\r
[    1.950839] vesafb: Truecolor: size=0:5:6:5, shift=0:11:5:0\r
[    1.956910] vesafb: framebuffer at 0xb0000000, mapped to 0xffffc90012680000, using 1875k, total 16384k\r
[    1.966392] bootsplash 3.2.0-2010/03/31: looking for picture...\r
[    1.966394] bootsplash: silentjpeg size 62784 bytes\r
[    1.973068] bootsplash: ...found (800x600, 32557 bytes, v3).\r
[    2.039455] Console: switching to colour frame buffer device 96x33\r
[    2.095362] fb0: VESA VGA frame buffer device\r
[    2.099880] Serial: 8250/16550 driver, 8 ports, IRQ sharing disabled\r
[    2.106347] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A\r
[    2.148103] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A\r
[    2.180650] 00:09: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A\r
[    2.249155] 00:0a: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A\r
[    2.255081] Non-volatile memory driver v1.3\r
[    2.259277] Linux agpgart interface v0.103\r
[    2.263508] Fixed MDIO Bus: probed\r
[    2.267000] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12\r
[    2.278376] serio: i8042 KBD port at 0x60,0x64 irq 1\r
[    2.283414] serio: i8042 AUX port at 0x60,0x64 irq 12\r
[    2.288632] mousedev: PS/2 mouse device common for all mice\r
[    2.294380] cpuidle: using governor ladder\r
[    2.298515] cpuidle: using governor menu\r
[    2.302473] EFI Variables Facility v0.08 2004-May-17\r
[    2.307781] TCP cubic registered\r
[    2.311069] Registering the dns_resolver key type\r
[    2.354426] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input0\r
[    2.363156] registered taskstats version 1\r
[    2.373012]   Magic number: 9:592:891\r
[    2.378973] Freeing unused kernel memory: 1344k freed\r
[    2.384536] Write protecting the kernel read-only data: 10240k\r
[    2.394861] Freeing unused kernel memory: 1708k freed\r
[    2.403205] Freeing unused kernel memory: 1008k freed\r
doing fast boot\r
[    2.465761] SCSI subsystem initialized\r
[    2.477850] ata_piix 0000:00:1f.1: PCI INT A -> GSI 20 (level, low) -> IRQ 20\r
[    2.485410] scsi0 : ata_piix\r
[    2.485415] Error handler scsi_eh_0 sleeping\r
[    2.492953] scsi1 : ata_piix\r
[    2.492957] Error handler scsi_eh_1 sleeping\r
[    2.501332] ata1: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x50b0 irq 14\r
[    2.508348] ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x50b8 irq 15\r
[    2.515365] ata_piix 0000:00:1f.2: PCI INT B -> GSI 20 (level, low) -> IRQ 20\r
[    2.515422] Error handler scsi_eh_0 waking up\r
[    2.515606] Error handler scsi_eh_1 waking up\r
[    2.531334] ata_piix 0000:00:1f.2: MAP [ P0 P2 P1 P3 ]\r
[    2.536951] scsi2 : ata_piix\r
[    2.536955] Error handler scsi_eh_2 sleeping\r
[    2.544297] scsi3 : ata_piix\r
[    2.544301] Error handler scsi_eh_3 sleeping\r
[    2.552498] ata3: SATA max UDMA/133 cmd 0x50c8 ctl 0x50e4 bmdma 0x50a0 irq 20\r
[    2.559662] ata4: SATA max UDMA/133 cmd 0x50c0 ctl 0x50e0 bmdma 0x50a8 irq 20\r
[    2.566920] Error handler scsi_eh_2 waking up\r
[    2.566963] Error handler scsi_eh_3 waking up\r
[    2.680172] ata1.00: ATAPI: HL-DT-STDVD-ROM GDR8164B, 0L06, max UDMA/33\r
[    2.680181] Error handler scsi_eh_1 sleeping\r
[    2.704219] ata1.00: configured for UDMA/33\r
[    2.709864] Error handler scsi_eh_0 sleeping\r
[    2.709958] scsi 0:0:0:0: Send:\r
[    2.709982] scsi 0:0:0:0: CDB: Inquiry: 12 00 00 00 24 00\r
[    2.714866] scsi 0:0:0:0: Done: SUCCESS\r
[    2.714870] scsi 0:0:0:0:  Result: hostbyte=DID_OK driverbyte=DRIVER_OK\r
[    2.714874] scsi 0:0:0:0: CDB: Inquiry: 12 00 00 00 24 00\r
[    2.714927] scsi 0:0:0:0: Send:\r
[    2.714930] scsi 0:0:0:0: CDB: Inquiry: 12 00 00 00 60 00\r
[    2.718873] scsi 0:0:0:0: Done: SUCCESS\r
[    2.718876] scsi 0:0:0:0:  Result: hostbyte=DID_OK driverbyte=DRIVER_OK\r
[    2.718880] scsi 0:0:0:0: CDB: Inquiry: 12 00 00 00 60 00\r
[    2.718925] scsi 0:0:0:0: CD-ROM            HL-DT-ST DVD-ROM GDR8164B 0L06 PQ: 0 ANSI: 5\r
[    2.732124] Error handler scsi_eh_3 sleeping\r
[    2.786482] Error handler scsi_eh_2 sleeping\r
[    2.803907] 3ware 9000 Storage Controller device driver for Linux v2.26.02.014.\r
[    2.811372] 3w-9xxx 0000:08:00.0: PCI INT A -> GSI 32 (level, low) -> IRQ 32\r
[    2.818544] Error handler scsi_eh_4 sleeping\r
[    2.884077] Refined TSC clocksource calibration: 2327.499 MHz.\r
[    2.889963] Switching to clocksource tsc\r
[    3.096026] scsi4 : 3ware 9000 Storage Controller\r
[    3.100828] 3w-9xxx: scsi4: Found a 3ware 9000 Storage Controller at 0xbad00000, IRQ: 32.\r
[    3.357006] input: ImExPS/2 Generic Explorer Mouse as /devices/platform/i8042/serio1/input/input1\r
[    3.444028] 3w-9xxx: scsi4: Firmware FE9X 4.10.00.027, BIOS BE9X 4.08.00.004, Ports: 8.\r
[    3.452146] scsi 4:0:0:0: Send:\r
[    3.455432] scsi 4:0:0:0: CDB: Inquiry: 12 00 00 00 24 00\r
[   24.800020] scsi 4:0:0:0: Done: TIMEOUT\r
[   24.803903] scsi 4:0:0:0:  Result: hostbyte=DID_OK driverbyte=DRIVER_OK\r
[   24.804015] scsi 4:0:0:0: CDB: Inquiry: 12 00 00 00 24 00\r
[   24.816159] Error handler scsi_eh_4 waking up\r
[   24.820556] Total of 1 commands on 1 devices require eh work\r
[   24.826249] scsi 4:0:0:0: WARNING: (0x06:0x002C): Command (0x12) timed out, resetting card.\r
[   49.932014] scsi 4:0:0:0: Send:\r
[   49.935314] scsi 4:0:0:0: CDB: Test Unit Ready: 00 00 00 00 00 00\r

[-- Attachment #3: Type: TEXT/plain, Size: 67104 bytes --]

gwstslesvmh02:~ # lspci -vvv\r
00:00.0 Host bridge: Intel Corporation 5000P Chipset Memory Controller Hub (rev b1)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Interrupt: pin A routed to IRQ 0\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit-\r
                Address: fee00000  Data: 0000\r
        Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 128 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise+ LLActRep+ BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-\r
                RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna- CRSVisible-\r
                RootCap: CRSVisible-\r
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES+ TLP+ FCP+ CmpltTO+ CmpltAbrt- UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol+\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-\r
\r
00:02.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x8 Port 2-3 (rev b1) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=00, secondary=01, subordinate=06, sec-latency=0\r
        I/O behind bridge: 00003000-00004fff\r
        Memory behind bridge: ba000000-babfffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit-\r
                Address: fee00000  Data: 0000\r
        Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 128 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #2, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise+ LLActRep+ BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-\r
                RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna- CRSVisible-\r
                RootCap: CRSVisible-\r
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UEMsk:  DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES+ TLP+ FCP+ CmpltTO+ CmpltAbrt- UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
00:03.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x4 Port 3 (rev b1) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=00, secondary=07, subordinate=07, sec-latency=0\r
        I/O behind bridge: 0000f000-00000fff\r
        Memory behind bridge: fff00000-000fffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit-\r
                Address: fee00000  Data: 0000\r
        Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 128 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #3, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise+ LLActRep+ BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-\r
                RootCap: CRSVisible-\r
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UEMsk:  DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
00:04.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x8 Port 4-5 (rev b1) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=00, secondary=08, subordinate=08, sec-latency=0\r
        I/O behind bridge: 00002000-00002fff\r
        Memory behind bridge: bad00000-badfffff\r
        Prefetchable memory behind bridge: 00000000b8000000-00000000b9ffffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit-\r
                Address: fee00000  Data: 0000\r
        Capabilities: [6c] Express (v1) Root Port (Slot+), MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 128 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #4, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise+ LLActRep+ BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-\r
                SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-\r
                        Slot #6, PowerLimit 25.000W; Interlock- NoCompl-\r
                SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-\r
                        Control: AttnInd Off, PwrInd On, Power- Interlock-\r
                SltSta: Status: AttnBtn- PowerFlt- MRL+ CmdCplt- PresDet+ Interlock-\r
                        Changed: MRL- PresDet- LinkState-\r
                RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna- CRSVisible-\r
                RootCap: CRSVisible-\r
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UEMsk:  DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES+ TLP+ FCP+ CmpltTO+ CmpltAbrt- UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
00:05.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x4 Port 5 (rev b1) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=00, secondary=09, subordinate=09, sec-latency=0\r
        I/O behind bridge: 0000f000-00000fff\r
        Memory behind bridge: fff00000-000fffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit-\r
                Address: fee00000  Data: 0000\r
        Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 128 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #5, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise+ LLActRep+ BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-\r
                RootCap: CRSVisible-\r
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UEMsk:  DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
00:06.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x8 Port 6-7 (rev b1) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=00, secondary=0a, subordinate=0a, sec-latency=0\r
        I/O behind bridge: 0000f000-00000fff\r
        Memory behind bridge: fff00000-000fffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit-\r
                Address: fee00000  Data: 0000\r
        Capabilities: [6c] Express (v1) Root Port (Slot+), MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 128 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #6, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise+ LLActRep+ BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
                SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-\r
                        Slot #5, PowerLimit 25.000W; Interlock- NoCompl-\r
                SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-\r
                        Control: AttnInd Off, PwrInd On, Power- Interlock-\r
                SltSta: Status: AttnBtn- PowerFlt- MRL+ CmdCplt- PresDet- Interlock-\r
                        Changed: MRL- PresDet+ LinkState-\r
                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-\r
                RootCap: CRSVisible-\r
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UEMsk:  DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
00:07.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x4 Port 7 (rev b1) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=00, secondary=0b, subordinate=0b, sec-latency=0\r
        I/O behind bridge: 0000f000-00000fff\r
        Memory behind bridge: fff00000-000fffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit-\r
                Address: fee00000  Data: 0000\r
        Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 128 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #7, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise+ LLActRep+ BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-\r
                RootCap: CRSVisible-\r
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UEMsk:  DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
00:08.0 System peripheral: Intel Corporation 5000 Series Chipset DMA Engine (rev b1)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Interrupt: pin A routed to IRQ 72\r
        Region 0: Memory at fe700000 (64-bit, non-prefetchable) [size=1K]\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [58] MSI: Enable+ Count=1/1 Maskable- 64bit-\r
                Address: fee0100c  Data: 4159\r
        Capabilities: [6c] Express (v1) Root Complex Integrated Endpoint, MSI 00\r
                DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 128 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us\r
                        ClockPM- Surprise- LLActRep- BwNot-\r
                LnkCtl: ASPM L1 Enabled; Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-\r
        Kernel driver in use: ioatdma\r
        Kernel modules: ioatdma\r
\r
00:10.0 Host bridge: Intel Corporation 5000 Series Chipset FSB Registers (rev b1)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Kernel driver in use: i5000_edac\r
        Kernel modules: i5k_amb, i5000_edac\r
\r
00:10.1 Host bridge: Intel Corporation 5000 Series Chipset FSB Registers (rev b1)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Kernel modules: i5k_amb, i5000_edac\r
\r
00:10.2 Host bridge: Intel Corporation 5000 Series Chipset FSB Registers (rev b1)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Kernel modules: i5k_amb, i5000_edac\r
\r
00:11.0 Host bridge: Intel Corporation 5000 Series Chipset Reserved Registers (rev b1)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
\r
00:13.0 Host bridge: Intel Corporation 5000 Series Chipset Reserved Registers (rev b1)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
\r
00:15.0 Host bridge: Intel Corporation 5000 Series Chipset FBD Registers (rev b1)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
\r
00:16.0 Host bridge: Intel Corporation 5000 Series Chipset FBD Registers (rev b1)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
\r
00:1c.0 PCI bridge: Intel Corporation 631xESB/632xESB/3100 Chipset PCI Express Root Port 1 (rev 09) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=00, secondary=0c, subordinate=0c, sec-latency=0\r
        I/O behind bridge: 00006000-00006fff\r
        Memory behind bridge: baf00000-bb0fffff\r
        Prefetchable memory behind bridge: 00000000bb100000-00000000bb2fffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00\r
                DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited\r
                        ExtTag+ RBE- FLReset-\r
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-\r
                        MaxPayload 128 bytes, MaxReadReq 128 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-\r
                LnkCap: Port #1, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <1us, L1 <4us\r
                        ClockPM- Surprise- LLActRep- BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
                SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+\r
                        Slot #4, PowerLimit 25.000W; Interlock- NoCompl-\r
                SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-\r
                        Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-\r
                SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-\r
                        Changed: MRL- PresDet- LinkState-\r
                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-\r
                RootCap: CRSVisible-\r
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-\r
        Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-\r
                Address: feeff00c  Data: 4141\r
        Capabilities: [90] Subsystem: Intel Corporation Device 3476\r
        Capabilities: [a0] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [100 v1] Virtual Channel\r
                Caps:   LPEVC=0 RefClk=100ns PATEntryBits=1\r
                Arb:    Fixed+ WRR32- WRR64- WRR128-\r
                Ctrl:   ArbSelect=Fixed\r
                Status: InProgress-\r
                VC0:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-\r
                        Arb:    Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-\r
                        Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff\r
                        Status: NegoPending- InProgress-\r
                VC1:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-\r
                        Arb:    Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-\r
                        Ctrl:   Enable- ID=0 ArbSelect=Fixed TC/VC=00\r
                        Status: NegoPending- InProgress-\r
        Capabilities: [180 v1] Root Complex Link\r
                Desc:   PortNumber=01 ComponentID=02 EltType=Config\r
                Link0:  Desc:   TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+\r
                        Addr:   00000000fed1c001\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
00:1d.0 USB controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #1 (rev 09) (prog-if 00 [UHCI])\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Interrupt: pin A routed to IRQ 23\r
        Region 4: I/O ports at 5080 [size=32]\r
        Kernel driver in use: uhci_hcd\r
        Kernel modules: uhci-hcd\r
\r
00:1d.1 USB controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #2 (rev 09) (prog-if 00 [UHCI])\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Interrupt: pin B routed to IRQ 22\r
        Region 4: I/O ports at 5060 [size=32]\r
        Kernel driver in use: uhci_hcd\r
        Kernel modules: uhci-hcd\r
\r
00:1d.2 USB controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #3 (rev 09) (prog-if 00 [UHCI])\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Interrupt: pin C routed to IRQ 23\r
        Region 4: I/O ports at 5040 [size=32]\r
        Kernel driver in use: uhci_hcd\r
        Kernel modules: uhci-hcd\r
\r
00:1d.3 USB controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #4 (rev 09) (prog-if 00 [UHCI])\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Interrupt: pin D routed to IRQ 22\r
        Region 4: I/O ports at 5020 [size=32]\r
        Kernel driver in use: uhci_hcd\r
        Kernel modules: uhci-hcd\r
\r
00:1d.7 USB controller: Intel Corporation 631xESB/632xESB/3100 Chipset EHCI USB2 Controller (rev 09) (prog-if 20 [EHCI])\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Interrupt: pin A routed to IRQ 23\r
        Region 0: Memory at bae00400 (32-bit, non-prefetchable) [size=1K]\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [58] Debug port: BAR=1 offset=00a0\r
        Kernel driver in use: ehci_hcd\r
        Kernel modules: ehci-hcd\r
\r
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev d9) (prog-if 01 [Subtractive decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Bus: primary=00, secondary=0d, subordinate=0d, sec-latency=32\r
        I/O behind bridge: 00001000-00001fff\r
        Memory behind bridge: bac00000-bacfffff\r
        Prefetchable memory behind bridge: 00000000b0000000-00000000b7ffffff\r
        Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn+\r
        Capabilities: [50] Subsystem: Intel Corporation Device 3476\r
\r
00:1f.0 ISA bridge: Intel Corporation 631xESB/632xESB/3100 Chipset LPC Interface Controller (rev 09)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Kernel modules: iTCO_wdt, intel-rng\r
\r
00:1f.1 IDE interface: Intel Corporation 631xESB/632xESB IDE Controller (rev 09) (prog-if 8a [Master SecP PriP])\r
        Subsystem: Intel Corporation Device 3476\r
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Interrupt: pin A routed to IRQ 20\r
        Region 0: I/O ports at 01f0 [size=8]\r
        Region 1: I/O ports at 03f4 [size=1]\r
        Region 2: I/O ports at 0170 [size=8]\r
        Region 3: I/O ports at 0374 [size=1]\r
        Region 4: I/O ports at 50b0 [size=16]\r
        Kernel driver in use: ata_piix\r
        Kernel modules: ata_generic, pata_acpi, ata_piix\r
\r
00:1f.2 IDE interface: Intel Corporation 631xESB/632xESB/3100 Chipset SATA IDE Controller (rev 09) (prog-if 8f [Master SecP SecO PriP PriO])\r
        Subsystem: Intel Corporation Device 3476\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0\r
        Interrupt: pin B routed to IRQ 20\r
        Region 0: I/O ports at 50c8 [size=8]\r
        Region 1: I/O ports at 50e4 [size=4]\r
        Region 2: I/O ports at 50c0 [size=8]\r
        Region 3: I/O ports at 50e0 [size=4]\r
        Region 4: I/O ports at 50a0 [size=16]\r
        Region 5: Memory at bae00000 (32-bit, non-prefetchable) [size=1K]\r
        Capabilities: [70] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Kernel driver in use: ata_piix\r
        Kernel modules: ata_generic, pata_acpi, ata_piix\r
\r
00:1f.3 SMBus: Intel Corporation 631xESB/632xESB/3100 Chipset SMBus Controller (rev 09)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Interrupt: pin B routed to IRQ 20\r
        Region 4: I/O ports at 5000 [size=32]\r
        Kernel driver in use: i801_smbus\r
        Kernel modules: i2c-i801\r
\r
01:00.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Upstream Port (rev 01) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=01, secondary=02, subordinate=04, sec-latency=0\r
        I/O behind bridge: 00004000-00004fff\r
        Memory behind bridge: ba000000-ba8fffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [44] Express (v1) Upstream Port, MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us\r
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-SlotPowerLimit 0.000W\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-\r
                        MaxPayload 128 bytes, MaxReadReq 4096 bytes\r
                DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend-\r
                LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise- LLActRep- BwNot-\r
                LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
        Capabilities: [70] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [80] Subsystem: Intel Corporation Device 3476\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
01:00.3 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express to PCI-X Bridge (rev 01) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=01, secondary=05, subordinate=06, sec-latency=48\r
        I/O behind bridge: 00003000-00003fff\r
        Memory behind bridge: ba900000-baafffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [44] Express (v1) PCI/PCI-X Bridge, MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us\r
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry-\r
                        MaxPayload 128 bytes, MaxReadReq 512 bytes\r
                DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend-\r
                LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise- LLActRep- BwNot-\r
                LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-\r
        Capabilities: [6c] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [80] Subsystem: Intel Corporation Device 3476\r
        Capabilities: [d8] PCI-X bridge device\r
                Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=conv\r
                Status: Dev=00:00.3 64bit- 133MHz- SCD- USC- SCO- SRD-\r
                Upstream: Capacity=65535 CommitmentLimit=65535\r
                Downstream: Capacity=65535 CommitmentLimit=65535\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel modules: shpchp\r
\r
02:00.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Downstream Port E1 (rev 01) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=02, secondary=03, subordinate=03, sec-latency=0\r
        I/O behind bridge: 0000f000-00000fff\r
        Memory behind bridge: fff00000-000fffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [44] Express (v1) Downstream Port (Slot-), MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-\r
                        MaxPayload 128 bytes, MaxReadReq 4096 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise- LLActRep- BwNot-\r
                LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
        Capabilities: [60] MSI: Enable- Count=1/1 Maskable- 64bit+\r
                Address: 0000000000000000  Data: 0000\r
        Capabilities: [70] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [80] Subsystem: Intel Corporation Device 3476\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
02:02.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Downstream Port E3 (rev 01) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Bus: primary=02, secondary=04, subordinate=04, sec-latency=0\r
        I/O behind bridge: 00004000-00004fff\r
        Memory behind bridge: ba000000-ba8fffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [44] Express (v1) Downstream Port (Slot-), MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us\r
                        ExtTag- RBE- FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-\r
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-\r
                        MaxPayload 128 bytes, MaxReadReq 4096 bytes\r
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-\r
                LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited\r
                        ClockPM- Surprise- LLActRep- BwNot-\r
                LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
        Capabilities: [60] MSI: Enable- Count=1/1 Maskable- 64bit+\r
                Address: 0000000000000000  Data: 0000\r
        Capabilities: [70] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [80] Subsystem: Intel Corporation Device 3476\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\r
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-\r
        Kernel driver in use: pcieport\r
        Kernel modules: shpchp\r
\r
04:00.0 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) (rev 01)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Interrupt: pin A routed to IRQ 70\r
        Region 0: Memory at ba820000 (32-bit, non-prefetchable) [size=128K]\r
        Region 1: Memory at ba400000 (32-bit, non-prefetchable) [size=4M]\r
        Region 2: I/O ports at 4020 [size=32]\r
        Capabilities: [c8] Power Management version 2\r
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-\r
        Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+\r
                Address: 00000000fee0400c  Data: 4169\r
        Capabilities: [e0] Express (v1) Endpoint, MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us\r
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+\r
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 512 bytes\r
                DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend-\r
                LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM unknown, Latency L0 <128ns, L1 <64us\r
                        ClockPM- Surprise- LLActRep- BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn-\r
        Capabilities: [140 v1] Device Serial Number 00-15-17-ff-ff-41-52-5c\r
        Kernel driver in use: e1000e\r
        Kernel modules: e1000e\r
\r
04:00.1 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) (rev 01)\r
        Subsystem: Intel Corporation Intel S5000PSLSATA Server Board\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Interrupt: pin B routed to IRQ 71\r
        Region 0: Memory at ba800000 (32-bit, non-prefetchable) [size=128K]\r
        Region 1: Memory at ba000000 (32-bit, non-prefetchable) [size=4M]\r
        Region 2: I/O ports at 4000 [size=32]\r
        Capabilities: [c8] Power Management version 2\r
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-\r
        Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+\r
                Address: 00000000fee0400c  Data: 4179\r
        Capabilities: [e0] Express (v1) Endpoint, MSI 00\r
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us\r
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+\r
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 512 bytes\r
                DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend-\r
                LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM unknown, Latency L0 <128ns, L1 <64us\r
                        ClockPM- Surprise- LLActRep- BwNot-\r
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\r
                AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn-\r
        Capabilities: [140 v1] Device Serial Number 00-15-17-ff-ff-41-52-5c\r
        Kernel driver in use: e1000e\r
        Kernel modules: e1000e\r
\r
05:01.0 Ethernet controller: Intel Corporation 82542 Gigabit Ethernet Controller (Fiber) (rev 03)\r
        Subsystem: Intel Corporation PRO/1000 Gigabit Server Adapter\r
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 32 (63750ns min), Cache Line Size: 64 bytes\r
        Interrupt: pin A routed to IRQ 25\r
        Region 0: Memory at baa00000 (32-bit, non-prefetchable) [size=128K]\r
        Capabilities: [dc] Power Management version 1\r
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Kernel driver in use: e1000\r
        Kernel modules: e1000\r
\r
05:02.0 PCI bridge: Pericom Semiconductor PI7C21P100 PCI to PCI Bridge (rev 01) (prog-if 00 [Normal decode])\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 32, Cache Line Size: 64 bytes\r
        Bus: primary=05, secondary=06, subordinate=06, sec-latency=64\r
        I/O behind bridge: 00003000-00003fff\r
        Memory behind bridge: ba900000-ba9fffff\r
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff\r
        Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR-\r
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-\r
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\r
        Capabilities: [80] PCI-X bridge device\r
                Secondary Status: 64bit+ 133MHz+ SCD- USC+ SCO- SRD- Freq=133MHz\r
                Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- SCO- SRD-\r
                Upstream: Capacity=32 CommitmentLimit=32\r
                Downstream: Capacity=32 CommitmentLimit=32\r
        Capabilities: [90] Power Management version 2\r
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Kernel modules: shpchp\r
\r
06:04.0 Ethernet controller: Intel Corporation 82546GB Gigabit Ethernet Controller (Copper) (rev 03)\r
        Subsystem: Intel Corporation PRO/1000 GT Quad Port Server Adapter\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 64 (63750ns min), Cache Line Size: 64 bytes\r
        Interrupt: pin A routed to IRQ 26\r
        Region 0: Memory at ba900000 (64-bit, non-prefetchable) [size=128K]\r
        Region 4: I/O ports at 30c0 [size=64]\r
        Capabilities: [dc] Power Management version 2\r
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-\r
        Capabilities: [e4] PCI-X non-bridge device\r
                Command: DPERE- ERO+ RBC=2048 OST=1\r
                Status: Dev=06:04.0 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz-\r
        Capabilities: [f0] MSI: Enable- Count=1/1 Maskable- 64bit+\r
                Address: 0000000000000000  Data: 0000\r
        Kernel driver in use: e1000\r
        Kernel modules: e1000\r
\r
06:04.1 Ethernet controller: Intel Corporation 82546GB Gigabit Ethernet Controller (Copper) (rev 03)\r
        Subsystem: Intel Corporation PRO/1000 GT Quad Port Server Adapter\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 64 (63750ns min), Cache Line Size: 64 bytes\r
        Interrupt: pin B routed to IRQ 27\r
        Region 0: Memory at ba920000 (64-bit, non-prefetchable) [size=128K]\r
        Region 4: I/O ports at 3080 [size=64]\r
        Capabilities: [dc] Power Management version 2\r
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-\r
        Capabilities: [e4] PCI-X non-bridge device\r
                Command: DPERE- ERO+ RBC=2048 OST=1\r
                Status: Dev=06:04.1 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz-\r
        Capabilities: [f0] MSI: Enable- Count=1/1 Maskable- 64bit+\r
                Address: 0000000000000000  Data: 0000\r
        Kernel driver in use: e1000\r
        Kernel modules: e1000\r
\r
06:06.0 Ethernet controller: Intel Corporation 82546GB Gigabit Ethernet Controller (Copper) (rev 03)\r
        Subsystem: Intel Corporation PRO/1000 GT Quad Port Server Adapter\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 64 (63750ns min), Cache Line Size: 64 bytes\r
        Interrupt: pin A routed to IRQ 24\r
        Region 0: Memory at ba940000 (64-bit, non-prefetchable) [size=128K]\r
        Region 4: I/O ports at 3040 [size=64]\r
        Capabilities: [dc] Power Management version 2\r
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-\r
        Capabilities: [e4] PCI-X non-bridge device\r
                Command: DPERE- ERO+ RBC=2048 OST=1\r
                Status: Dev=06:06.0 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz-\r
        Capabilities: [f0] MSI: Enable- Count=1/1 Maskable- 64bit+\r
                Address: 0000000000000000  Data: 0000\r
        Kernel driver in use: e1000\r
        Kernel modules: e1000\r
\r
06:06.1 Ethernet controller: Intel Corporation 82546GB Gigabit Ethernet Controller (Copper) (rev 03)\r
        Subsystem: Intel Corporation PRO/1000 GT Quad Port Server Adapter\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-\r
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 64 (63750ns min), Cache Line Size: 64 bytes\r
        Interrupt: pin B routed to IRQ 25\r
        Region 0: Memory at ba960000 (64-bit, non-prefetchable) [size=128K]\r
        Region 4: I/O ports at 3000 [size=64]\r
        Capabilities: [dc] Power Management version 2\r
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-\r
        Capabilities: [e4] PCI-X non-bridge device\r
                Command: DPERE- ERO+ RBC=2048 OST=1\r
                Status: Dev=06:06.1 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz-\r
        Capabilities: [f0] MSI: Enable- Count=1/1 Maskable- 64bit+\r
                Address: 0000000000000000  Data: 0000\r
        Kernel driver in use: e1000\r
        Kernel modules: e1000\r
\r
08:00.0 RAID bus controller: 3ware Inc 9650SE SATA-II RAID PCIe (rev 01)\r
        Subsystem: 3ware Inc 9650SE SATA-II RAID PCIe\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+\r
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 0, Cache Line Size: 64 bytes\r
        Interrupt: pin A routed to IRQ 32\r
        Region 0: Memory at b8000000 (64-bit, prefetchable) [size=32M]\r
        Region 2: Memory at bad00000 (64-bit, non-prefetchable) [size=4K]\r
        Region 4: I/O ports at 2000 [size=256]\r
        Expansion ROM at bad20000 [disabled] [size=128K]\r
        Capabilities: [40] Power Management version 2\r
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Capabilities: [50] MSI: Enable+ Count=1/32 Maskable- 64bit+\r
                Address: 00000000fec80020  Data: 0008\r
        Capabilities: [70] Express (v1) Legacy Endpoint, MSI 00\r
                DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <128ns, L1 <2us\r
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-\r
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-\r
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+\r
                        MaxPayload 128 bytes, MaxReadReq 512 bytes\r
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-\r
                LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s L1, Latency L0 <512ns, L1 <64us\r
                        ClockPM- Surprise- LLActRep+ BwNot-\r
                LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk-\r
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\r
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk- DLActive+ BWMgmt- ABWMgmt-\r
        Capabilities: [100 v1] Advanced Error Reporting\r
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-\r
                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\r
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+\r
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+\r
                AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-\r
        Kernel driver in use: 3w-9xxx\r
        Kernel modules: 3w-9xxx\r
\r
0d:0c.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02) (prog-if 00 [VGA controller])\r
        Subsystem: Intel Corporation S5000PSLSATA Server Board\r
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B+ DisINTx-\r
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\r
        Latency: 32 (2000ns min), Cache Line Size: 64 bytes\r
        Interrupt: pin A routed to IRQ 11\r
        Region 0: Memory at b0000000 (32-bit, prefetchable) [size=128M]\r
        Region 1: I/O ports at 1000 [size=256]\r
        Region 2: Memory at bac00000 (32-bit, non-prefetchable) [size=64K]\r
        Expansion ROM at bac20000 [disabled] [size=128K]\r
        Capabilities: [50] Power Management version 2\r
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)\r
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\r
        Kernel modules: radeonfb\r

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-10-30 10:27             ` Jiri Kosina
@ 2013-10-31 21:27               ` Bjorn Helgaas
  2013-11-05 13:06                 ` Jiri Kosina
  0 siblings, 1 reply; 14+ messages in thread
From: Bjorn Helgaas @ 2013-10-31 21:27 UTC (permalink / raw)
  To: Jiri Kosina
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

On Wed, Oct 30, 2013 at 4:27 AM, Jiri Kosina <jkosina@suse.cz> wrote:
> Attached is dmesg output leading to timeouts (that are cured by my
> original patch in this thread) and lspci.

I opened https://bugzilla.kernel.org/show_bug.cgi?id=64141 for this
issue and attached your dmesg log and lspci output.

> Please let me know if there is anything else I could do, or if you are
> going to proceed with my patch adding the quirk.

Your quirk keeps us from disabling MSIs on the device during
enumeration.  But even if the BIOS left MSIs enabled, there's nothing
to field the MSI until after the driver claims the device.  So I don't
believe this has to be done as a quirk.  It should work just as well
to do something in the driver when it claims the device.

I guess another way to say this is that I don't think we understand
what the real problem is, and if we just add a quirk to work around
it, we might miss the chance to fix the real problem, and we may never
be able to remove the special-case code we're adding in the generic
path.

I know you said you tried doing something in the driver, and it didn't
work.  I don't know exactly what you tried, but twa_probe() looks
strange to me.  The other drivers I looked at do all their PCI
initialization before the scsi_host_alloc() / scsi_add_host() /
scsi_scan_host() stuff.  But twa_probe() has PCI stuff scattered
around between those three SCSI calls.  In particular, it does the MSI
setup way down near the end, after scsi_add_host(), which seems like
just the sort of thing that could explain this problem.

Bjorn

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-10-31 21:27               ` Bjorn Helgaas
@ 2013-11-05 13:06                 ` Jiri Kosina
  2013-11-05 18:44                   ` Bjorn Helgaas
  0 siblings, 1 reply; 14+ messages in thread
From: Jiri Kosina @ 2013-11-05 13:06 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

On Thu, 31 Oct 2013, Bjorn Helgaas wrote:

> > Attached is dmesg output leading to timeouts (that are cured by my
> > original patch in this thread) and lspci.
> 
> I opened https://bugzilla.kernel.org/show_bug.cgi?id=64141 for this
> issue and attached your dmesg log and lspci output.
> 
> > Please let me know if there is anything else I could do, or if you are
> > going to proceed with my patch adding the quirk.
> 
> Your quirk keeps us from disabling MSIs on the device during
> enumeration.  But even if the BIOS left MSIs enabled, there's nothing
> to field the MSI until after the driver claims the device.  So I don't
> believe this has to be done as a quirk.  It should work just as well
> to do something in the driver when it claims the device.
> 
> I guess another way to say this is that I don't think we understand
> what the real problem is, and if we just add a quirk to work around
> it, we might miss the chance to fix the real problem, and we may never
> be able to remove the special-case code we're adding in the generic
> path.
> 
> I know you said you tried doing something in the driver, and it didn't
> work.  I don't know exactly what you tried, but twa_probe() looks
> strange to me.  The other drivers I looked at do all their PCI
> initialization before the scsi_host_alloc() / scsi_add_host() /
> scsi_scan_host() stuff.  But twa_probe() has PCI stuff scattered
> around between those three SCSI calls.  In particular, it does the MSI
> setup way down near the end, after scsi_add_host(), which seems like
> just the sort of thing that could explain this problem.

What I tried was patch below, but it didn't have any observable effect -- 
the commands sent to the controller would still time out the same way.

Debugging this is not really straightforward for me unfortunately, as I 
don't own the system myself.

I agree that we don't fully understand what is happening, but the quirk 
was the only way I have been able to come up with to make the device 
functioning again (apart from reverting d5dea7d95).

Any other ideas are welcome.

---
 drivers/scsi/3w-9xxx.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/scsi/3w-9xxx.c b/drivers/scsi/3w-9xxx.c
index ba754c3..bad7faf 100644
--- a/drivers/scsi/3w-9xxx.c
+++ b/drivers/scsi/3w-9xxx.c
@@ -2055,6 +2055,11 @@ static int __devinit twa_probe(struct pci_dev *pdev, const struct pci_device_id
 			goto out_disable_device;
 		}
 
+	/* Try to enable MSI */
+	if (use_msi && (pdev->device != PCI_DEVICE_ID_3WARE_9000) &&
+	    !pci_enable_msi(pdev))
+		set_bit(TW_USING_MSI, &tw_dev->flags);
+
 	host = scsi_host_alloc(&driver_template, sizeof(TW_Device_Extension));
 	if (!host) {
 		TW_PRINTK(host, TW_DRIVER, 0x24, "Failed to allocate memory for device extension");
@@ -2134,11 +2139,6 @@ static int __devinit twa_probe(struct pci_dev *pdev, const struct pci_device_id
 	       le32_to_cpu(*(int *)twa_get_param(tw_dev, 2, TW_INFORMATION_TABLE,
 				     TW_PARAM_PORTCOUNT, TW_PARAM_PORTCOUNT_LENGTH)));
 
-	/* Try to enable MSI */
-	if (use_msi && (pdev->device != PCI_DEVICE_ID_3WARE_9000) &&
-	    !pci_enable_msi(pdev))
-		set_bit(TW_USING_MSI, &tw_dev->flags);
-
 	/* Now setup the interrupt handler */
 	retval = request_irq(pdev->irq, twa_interrupt, IRQF_SHARED, "3w-9xxx", tw_dev);
 	if (retval) {


-- 
Jiri Kosina
SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-11-05 13:06                 ` Jiri Kosina
@ 2013-11-05 18:44                   ` Bjorn Helgaas
  2014-06-03 23:00                     ` Bjorn Helgaas
  0 siblings, 1 reply; 14+ messages in thread
From: Bjorn Helgaas @ 2013-11-05 18:44 UTC (permalink / raw)
  To: Jiri Kosina
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

On Tue, Nov 5, 2013 at 6:06 AM, Jiri Kosina <jkosina@suse.cz> wrote:
> On Thu, 31 Oct 2013, Bjorn Helgaas wrote:
>
>> > Attached is dmesg output leading to timeouts (that are cured by my
>> > original patch in this thread) and lspci.
>>
>> I opened https://bugzilla.kernel.org/show_bug.cgi?id=64141 for this
>> issue and attached your dmesg log and lspci output.
>>
>> > Please let me know if there is anything else I could do, or if you are
>> > going to proceed with my patch adding the quirk.
>>
>> Your quirk keeps us from disabling MSIs on the device during
>> enumeration.  But even if the BIOS left MSIs enabled, there's nothing
>> to field the MSI until after the driver claims the device.  So I don't
>> believe this has to be done as a quirk.  It should work just as well
>> to do something in the driver when it claims the device.
>>
>> I guess another way to say this is that I don't think we understand
>> what the real problem is, and if we just add a quirk to work around
>> it, we might miss the chance to fix the real problem, and we may never
>> be able to remove the special-case code we're adding in the generic
>> path.
>>
>> I know you said you tried doing something in the driver, and it didn't
>> work.  I don't know exactly what you tried, but twa_probe() looks
>> strange to me.  The other drivers I looked at do all their PCI
>> initialization before the scsi_host_alloc() / scsi_add_host() /
>> scsi_scan_host() stuff.  But twa_probe() has PCI stuff scattered
>> around between those three SCSI calls.  In particular, it does the MSI
>> setup way down near the end, after scsi_add_host(), which seems like
>> just the sort of thing that could explain this problem.
>
> What I tried was patch below, but it didn't have any observable effect --
> the commands sent to the controller would still time out the same way.
>
> Debugging this is not really straightforward for me unfortunately, as I
> don't own the system myself.
>
> I agree that we don't fully understand what is happening, but the quirk
> was the only way I have been able to come up with to make the device
> functioning again (apart from reverting d5dea7d95).
>
> Any other ideas are welcome.

This patch looks like a good start, but there's a whole lot of other
PCI-related initialization that I would suggest moving as well --
pci_request_regions(), ioremap(), pci_set_drvdata(), pci_enable_msi,
request_irq(), etc.  I would do this myself, but there are some pieces
that don't look completely trivial, e.g., things like
TW_DISABLE_INTERRUPTS() and twa_reset_sequence() don't look like
they're SCSI-specific, but they are currently implemented using
tw_dev, which looks like it's allocated by scsi_host_alloc().
Untangling all this looks like more work than I want to sign up to.

But I really don't want to put the quirk in because it's just a quick
hack that apparently just covers up bugs in the driver, and it will be
an annoyance in the PCI core forever.

Bjorn

> ---
>  drivers/scsi/3w-9xxx.c |   10 +++++-----
>  1 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/scsi/3w-9xxx.c b/drivers/scsi/3w-9xxx.c
> index ba754c3..bad7faf 100644
> --- a/drivers/scsi/3w-9xxx.c
> +++ b/drivers/scsi/3w-9xxx.c
> @@ -2055,6 +2055,11 @@ static int __devinit twa_probe(struct pci_dev *pdev, const struct pci_device_id
>                         goto out_disable_device;
>                 }
>
> +       /* Try to enable MSI */
> +       if (use_msi && (pdev->device != PCI_DEVICE_ID_3WARE_9000) &&
> +           !pci_enable_msi(pdev))
> +               set_bit(TW_USING_MSI, &tw_dev->flags);
> +
>         host = scsi_host_alloc(&driver_template, sizeof(TW_Device_Extension));
>         if (!host) {
>                 TW_PRINTK(host, TW_DRIVER, 0x24, "Failed to allocate memory for device extension");
> @@ -2134,11 +2139,6 @@ static int __devinit twa_probe(struct pci_dev *pdev, const struct pci_device_id
>                le32_to_cpu(*(int *)twa_get_param(tw_dev, 2, TW_INFORMATION_TABLE,
>                                      TW_PARAM_PORTCOUNT, TW_PARAM_PORTCOUNT_LENGTH)));
>
> -       /* Try to enable MSI */
> -       if (use_msi && (pdev->device != PCI_DEVICE_ID_3WARE_9000) &&
> -           !pci_enable_msi(pdev))
> -               set_bit(TW_USING_MSI, &tw_dev->flags);
> -
>         /* Now setup the interrupt handler */
>         retval = request_irq(pdev->irq, twa_interrupt, IRQF_SHARED, "3w-9xxx", tw_dev);
>         if (retval) {
>
>
> --
> Jiri Kosina
> SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2013-11-05 18:44                   ` Bjorn Helgaas
@ 2014-06-03 23:00                     ` Bjorn Helgaas
  2014-06-04  7:59                       ` Jiri Kosina
  0 siblings, 1 reply; 14+ messages in thread
From: Bjorn Helgaas @ 2014-06-03 23:00 UTC (permalink / raw)
  To: Jiri Kosina
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Adam Radford

On Tue, Nov 5, 2013 at 11:44 AM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> On Tue, Nov 5, 2013 at 6:06 AM, Jiri Kosina <jkosina@suse.cz> wrote:
>> On Thu, 31 Oct 2013, Bjorn Helgaas wrote:
>>
>>> > Attached is dmesg output leading to timeouts (that are cured by my
>>> > original patch in this thread) and lspci.
>>>
>>> I opened https://bugzilla.kernel.org/show_bug.cgi?id=64141 for this
>>> issue and attached your dmesg log and lspci output.
>>>
>>> > Please let me know if there is anything else I could do, or if you are
>>> > going to proceed with my patch adding the quirk.
>>>
>>> Your quirk keeps us from disabling MSIs on the device during
>>> enumeration.  But even if the BIOS left MSIs enabled, there's nothing
>>> to field the MSI until after the driver claims the device.  So I don't
>>> believe this has to be done as a quirk.  It should work just as well
>>> to do something in the driver when it claims the device.
>>>
>>> I guess another way to say this is that I don't think we understand
>>> what the real problem is, and if we just add a quirk to work around
>>> it, we might miss the chance to fix the real problem, and we may never
>>> be able to remove the special-case code we're adding in the generic
>>> path.
>>>
>>> I know you said you tried doing something in the driver, and it didn't
>>> work.  I don't know exactly what you tried, but twa_probe() looks
>>> strange to me.  The other drivers I looked at do all their PCI
>>> initialization before the scsi_host_alloc() / scsi_add_host() /
>>> scsi_scan_host() stuff.  But twa_probe() has PCI stuff scattered
>>> around between those three SCSI calls.  In particular, it does the MSI
>>> setup way down near the end, after scsi_add_host(), which seems like
>>> just the sort of thing that could explain this problem.
>>
>> What I tried was patch below, but it didn't have any observable effect --
>> the commands sent to the controller would still time out the same way.
>>
>> Debugging this is not really straightforward for me unfortunately, as I
>> don't own the system myself.
>>
>> I agree that we don't fully understand what is happening, but the quirk
>> was the only way I have been able to come up with to make the device
>> functioning again (apart from reverting d5dea7d95).
>>
>> Any other ideas are welcome.
>
> This patch looks like a good start, but there's a whole lot of other
> PCI-related initialization that I would suggest moving as well --
> pci_request_regions(), ioremap(), pci_set_drvdata(), pci_enable_msi,
> request_irq(), etc.  I would do this myself, but there are some pieces
> that don't look completely trivial, e.g., things like
> TW_DISABLE_INTERRUPTS() and twa_reset_sequence() don't look like
> they're SCSI-specific, but they are currently implemented using
> tw_dev, which looks like it's allocated by scsi_host_alloc().
> Untangling all this looks like more work than I want to sign up to.
>
> But I really don't want to put the quirk in because it's just a quick
> hack that apparently just covers up bugs in the driver, and it will be
> an annoyance in the PCI core forever.

Just FYI, I reassigned
https://bugzilla.kernel.org/show_bug.cgi?id=64141 from PCI to SCSI,
since I don't think there's a PCI core problem here.  I don't know if
SCSI pay attention to bugzilla at all; I'm just mentioning it here in
case anybody still cares about this problem and was hoping that I was
going to do something.

Bjorn

>> ---
>>  drivers/scsi/3w-9xxx.c |   10 +++++-----
>>  1 files changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/scsi/3w-9xxx.c b/drivers/scsi/3w-9xxx.c
>> index ba754c3..bad7faf 100644
>> --- a/drivers/scsi/3w-9xxx.c
>> +++ b/drivers/scsi/3w-9xxx.c
>> @@ -2055,6 +2055,11 @@ static int __devinit twa_probe(struct pci_dev *pdev, const struct pci_device_id
>>                         goto out_disable_device;
>>                 }
>>
>> +       /* Try to enable MSI */
>> +       if (use_msi && (pdev->device != PCI_DEVICE_ID_3WARE_9000) &&
>> +           !pci_enable_msi(pdev))
>> +               set_bit(TW_USING_MSI, &tw_dev->flags);
>> +
>>         host = scsi_host_alloc(&driver_template, sizeof(TW_Device_Extension));
>>         if (!host) {
>>                 TW_PRINTK(host, TW_DRIVER, 0x24, "Failed to allocate memory for device extension");
>> @@ -2134,11 +2139,6 @@ static int __devinit twa_probe(struct pci_dev *pdev, const struct pci_device_id
>>                le32_to_cpu(*(int *)twa_get_param(tw_dev, 2, TW_INFORMATION_TABLE,
>>                                      TW_PARAM_PORTCOUNT, TW_PARAM_PORTCOUNT_LENGTH)));
>>
>> -       /* Try to enable MSI */
>> -       if (use_msi && (pdev->device != PCI_DEVICE_ID_3WARE_9000) &&
>> -           !pci_enable_msi(pdev))
>> -               set_bit(TW_USING_MSI, &tw_dev->flags);
>> -
>>         /* Now setup the interrupt handler */
>>         retval = request_irq(pdev->irq, twa_interrupt, IRQF_SHARED, "3w-9xxx", tw_dev);
>>         if (retval) {
>>
>>
>> --
>> Jiri Kosina
>> SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] PCI: add quirk for 3ware 9650SE controller
  2014-06-03 23:00                     ` Bjorn Helgaas
@ 2014-06-04  7:59                       ` Jiri Kosina
  0 siblings, 0 replies; 14+ messages in thread
From: Jiri Kosina @ 2014-06-04  7:59 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: linux-kernel, linux-pci, linux-scsi, Eric W. Biederman,
	Jesse Barnes, Ales Novak, Adam Radford

On Tue, 3 Jun 2014, Bjorn Helgaas wrote:

> >>> > Attached is dmesg output leading to timeouts (that are cured by my
> >>> > original patch in this thread) and lspci.
> >>>
> >>> I opened https://bugzilla.kernel.org/show_bug.cgi?id=64141 for this
> >>> issue and attached your dmesg log and lspci output.
> >>>
> >>> > Please let me know if there is anything else I could do, or if you are
> >>> > going to proceed with my patch adding the quirk.
> >>>
> >>> Your quirk keeps us from disabling MSIs on the device during
> >>> enumeration.  But even if the BIOS left MSIs enabled, there's nothing
> >>> to field the MSI until after the driver claims the device.  So I don't
> >>> believe this has to be done as a quirk.  It should work just as well
> >>> to do something in the driver when it claims the device.
> >>>
> >>> I guess another way to say this is that I don't think we understand
> >>> what the real problem is, and if we just add a quirk to work around
> >>> it, we might miss the chance to fix the real problem, and we may never
> >>> be able to remove the special-case code we're adding in the generic
> >>> path.
> >>>
> >>> I know you said you tried doing something in the driver, and it didn't
> >>> work.  I don't know exactly what you tried, but twa_probe() looks
> >>> strange to me.  The other drivers I looked at do all their PCI
> >>> initialization before the scsi_host_alloc() / scsi_add_host() /
> >>> scsi_scan_host() stuff.  But twa_probe() has PCI stuff scattered
> >>> around between those three SCSI calls.  In particular, it does the MSI
> >>> setup way down near the end, after scsi_add_host(), which seems like
> >>> just the sort of thing that could explain this problem.
> >>
> >> What I tried was patch below, but it didn't have any observable effect --
> >> the commands sent to the controller would still time out the same way.
> >>
> >> Debugging this is not really straightforward for me unfortunately, as I
> >> don't own the system myself.
> >>
> >> I agree that we don't fully understand what is happening, but the quirk
> >> was the only way I have been able to come up with to make the device
> >> functioning again (apart from reverting d5dea7d95).
> >>
> >> Any other ideas are welcome.
> >
> > This patch looks like a good start, but there's a whole lot of other
> > PCI-related initialization that I would suggest moving as well --
> > pci_request_regions(), ioremap(), pci_set_drvdata(), pci_enable_msi,
> > request_irq(), etc.  I would do this myself, but there are some pieces
> > that don't look completely trivial, e.g., things like
> > TW_DISABLE_INTERRUPTS() and twa_reset_sequence() don't look like
> > they're SCSI-specific, but they are currently implemented using
> > tw_dev, which looks like it's allocated by scsi_host_alloc().
> > Untangling all this looks like more work than I want to sign up to.
> >
> > But I really don't want to put the quirk in because it's just a quick
> > hack that apparently just covers up bugs in the driver, and it will be
> > an annoyance in the PCI core forever.
> 
> Just FYI, I reassigned
> https://bugzilla.kernel.org/show_bug.cgi?id=64141 from PCI to SCSI,
> since I don't think there's a PCI core problem here.  I don't know if
> SCSI pay attention to bugzilla at all; I'm just mentioning it here in
> case anybody still cares about this problem and was hoping that I was
> going to do something.

I am adding to CC Ales Novak, who has been handling this bug on our side 
lately.

> 
> Bjorn
> 
> >> ---
> >>  drivers/scsi/3w-9xxx.c |   10 +++++-----
> >>  1 files changed, 5 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/scsi/3w-9xxx.c b/drivers/scsi/3w-9xxx.c
> >> index ba754c3..bad7faf 100644
> >> --- a/drivers/scsi/3w-9xxx.c
> >> +++ b/drivers/scsi/3w-9xxx.c
> >> @@ -2055,6 +2055,11 @@ static int __devinit twa_probe(struct pci_dev *pdev, const struct pci_device_id
> >>                         goto out_disable_device;
> >>                 }
> >>
> >> +       /* Try to enable MSI */
> >> +       if (use_msi && (pdev->device != PCI_DEVICE_ID_3WARE_9000) &&
> >> +           !pci_enable_msi(pdev))
> >> +               set_bit(TW_USING_MSI, &tw_dev->flags);
> >> +
> >>         host = scsi_host_alloc(&driver_template, sizeof(TW_Device_Extension));
> >>         if (!host) {
> >>                 TW_PRINTK(host, TW_DRIVER, 0x24, "Failed to allocate memory for device extension");
> >> @@ -2134,11 +2139,6 @@ static int __devinit twa_probe(struct pci_dev *pdev, const struct pci_device_id
> >>                le32_to_cpu(*(int *)twa_get_param(tw_dev, 2, TW_INFORMATION_TABLE,
> >>                                      TW_PARAM_PORTCOUNT, TW_PARAM_PORTCOUNT_LENGTH)));
> >>
> >> -       /* Try to enable MSI */
> >> -       if (use_msi && (pdev->device != PCI_DEVICE_ID_3WARE_9000) &&
> >> -           !pci_enable_msi(pdev))
> >> -               set_bit(TW_USING_MSI, &tw_dev->flags);
> >> -
> >>         /* Now setup the interrupt handler */
> >>         retval = request_irq(pdev->irq, twa_interrupt, IRQF_SHARED, "3w-9xxx", tw_dev);
> >>         if (retval) {
> >>
> >>
> >> --
> >> Jiri Kosina
> >> SUSE Labs
> 

-- 
Jiri Kosina
SUSE Labs

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2014-06-04  8:00 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-08-27  9:44 [PATCH] PCI: add quirk for 3ware 9650SE controller Jiri Kosina
2013-08-27  9:45 ` Jiri Kosina
2013-08-28 15:46   ` Jiri Kosina
2013-08-28 16:33     ` Bjorn Helgaas
2013-09-06  9:51       ` Jiri Kosina
2013-09-06 22:47         ` Bjorn Helgaas
2013-09-24 20:50           ` Bjorn Helgaas
2013-09-27  9:08           ` Jiri Kosina
2013-10-30 10:27             ` Jiri Kosina
2013-10-31 21:27               ` Bjorn Helgaas
2013-11-05 13:06                 ` Jiri Kosina
2013-11-05 18:44                   ` Bjorn Helgaas
2014-06-03 23:00                     ` Bjorn Helgaas
2014-06-04  7:59                       ` Jiri Kosina

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