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From: Victor Kamensky <kamensky@cisco.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	openembedded-core <openembedded-core@lists.openembedded.org>
Subject: Re: Need arm64/qemu help
Date: Mon, 19 Mar 2018 19:22:32 -0700 (PDT)	[thread overview]
Message-ID: <alpine.LRH.2.00.1803191917040.58477@sjc-ads-6991.cisco.com> (raw)
In-Reply-To: <e15e3ca1-ee9e-1efa-2247-2789aac05091@linaro.org>

[-- Attachment #1: Type: TEXT/PLAIN, Size: 2429 bytes --]



On Mon, 19 Mar 2018, Richard Henderson wrote:

> On 03/20/2018 07:24 AM, Victor Kamensky wrote:
>>> target/arm/translate-a64.c:handle_sys() is setting
>>>    s->base.is_jmp = DISAS_UPDATE;
>>> which it thinks will end the TB, specifically because system
>>> register writes might do things like unmask interrupts or
>>> otherwise require main loop processing.
>>>
>>> The changes that prompted b29fd33db578dec stopped this working.
>>> I suspect what we want is for the case DISAS_UPDATE in
>>> aarch64_tr_tb_stop() to fall through into DISAS_EXIT, not
>>> DISAS_JUMP. (The AArch32 code gets this right, amazingly.)
>>
>> Peter, thank you. I can confirm that change you suggested
>> like one below, boots fine.
>>
>> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
>> index 625ef2d..c381091 100644
>> --- a/target/arm/translate-a64.c
>> +++ b/target/arm/translate-a64.c
>> @@ -11384,12 +11384,12 @@ static void aarch64_tr_tb_stop(DisasContextBase
>> *dcbase, CPUState *cpu)
>>          case DISAS_UPDATE:
>>              gen_a64_set_pc_im(dc->pc);
>>              /* fall through */
>> -        case DISAS_JUMP:
>> -            tcg_gen_lookup_and_goto_ptr();
>> -            break;
>>          case DISAS_EXIT:
>>              tcg_gen_exit_tb(0);
>>              break;
>> +        case DISAS_JUMP:
>> +            tcg_gen_lookup_and_goto_ptr();
>> +            break;
>>          case DISAS_NORETURN:
>>          case DISAS_SWI:
>>              break;
>
> Alex and I just had a long chat about this, and I think this is the right solution.
>
> (1) It brings aa64 into alignment with aa32 wrt the meaning of these
> enumerators, (2) The only use of DISAS_UPDATE is there in handle_sys, so we're
> not changing the behaviour of any other insns, (3) The most frequent writes to
> system registers -- NZCV and FPCR -- are already special cased so that they
> won't exit the TB.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks, Richard. So how do we go about committing it in qemu tree?
Should I submit the patch or Alex or Peter will do it?

Once fix is in qemu tree I will pick it and submit patch for OE tree
on top of current qemu-2.11.1.

Thanks,
Victor

>
> r~
>

  parent reply	other threads:[~2018-03-20  2:22 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-03  9:00 Need arm64/qemu help Richard Purdie
2018-03-03 10:51 ` Ian Arkver
2018-03-03 11:06   ` Richard Purdie
2018-03-03 11:13   ` Ian Arkver
2018-03-11  0:11     ` Victor Kamensky
2018-03-11 14:05       ` Richard Purdie
     [not found]       ` <CAFEAcA-d6-_tVRWKbZpVsQtece4fjuUqF+o+-m-AG4jPUHPY4g@mail.gmail.com>
2018-03-12  2:25         ` Victor Kamensky
2018-03-17 22:51           ` Victor Kamensky
     [not found]             ` <87a7v4kj5g.fsf@linaro.org>
2018-03-19  6:26               ` Victor Kamensky
     [not found]                 ` <87605sjvk4.fsf@linaro.org>
2018-03-19 17:46                   ` Victor Kamensky
     [not found]                     ` <CAFEAcA8p9uO_7MXzkqyAnc-gifTHhmUgyRyE8X7hZnW=sbgQOg@mail.gmail.com>
2018-03-19 23:24                       ` Victor Kamensky
     [not found]                         ` <e15e3ca1-ee9e-1efa-2247-2789aac05091@linaro.org>
2018-03-20  2:22                           ` Victor Kamensky [this message]
     [not found]                       ` <874llbk1xc.fsf@linaro.org>
2018-03-20  2:14                         ` Victor Kamensky
2018-03-03 18:21 ` Richard Purdie
2018-03-05 22:10   ` Ian Arkver

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