From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Tomsich Subject: Re: [U-Boot,1/8] adc: Add driver for Rockchip Saradc Date: Wed, 13 Sep 2017 22:40:27 +0200 (CEST) Message-ID: References: <1505297379-12638-2-git-send-email-david.wu@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1505297379-12638-2-git-send-email-david.wu@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To: David Wu Cc: huangtao@rock-chips.com, linux-rockchip@lists.infradead.org, zhangqing@rock-chips.com, u-boot@lists.denx.de, p.marczak@samsung.com, andy.yan@rock-chips.com, chenjh@rock-chips.com List-Id: linux-rockchip.vger.kernel.org CgpPbiBXZWQsIDEzIFNlcCAyMDE3LCBEYXZpZCBXdSB3cm90ZToKCj4gVGhlIEFEQyBjYW4gc3Vw cG9ydCBzb21lIGNoYW5uZWxzIHNpZ25hbC1lbmRlZCBzb21lIGJpdHMgU3VjY2Vzc2l2ZSBBcHBy b3hpbWF0aW9uCj4gUmVnaXN0ZXIgKFNBUikgQS9EIENvbnZlcnRlciwgbGlrZSA2LWNoYW5uZWwg YW5kIDEwLWJpdC4gSXQgY29udmVydHMgdGhlIGFuYWxvZwo+IGlucHV0IHNpZ25hbCBpbnRvIHNv bWUgYml0cyBiaW5hcnkgZGlnaXRhbCBjb2Rlcy4KPgo+IFNpZ25lZC1vZmYtYnk6IERhdmlkIFd1 IDxkYXZpZC53dUByb2NrLWNoaXBzLmNvbT4KClJldmlld2VkLWJ5OiBQaGlsaXBwIFRvbXNpY2gg PHBoaWxpcHAudG9tc2ljaEB0aGVvYnJvbWEtc3lzdGVtcy5jb20+CgpQbGVhc2Ugc2VlIGJlbG93 IGZvciByZXF1ZXN0ZWQgY2hhbmdlcy4KCj4gLS0tCj4gZHJpdmVycy9hZGMvS2NvbmZpZyAgICAg ICAgICAgfCAgIDkgKysKPiBkcml2ZXJzL2FkYy9NYWtlZmlsZSAgICAgICAgICB8ICAgMSArCj4g ZHJpdmVycy9hZGMvcm9ja2NoaXAtc2FyYWRjLmMgfCAxODggKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrCj4gMyBmaWxlcyBjaGFuZ2VkLCAxOTggaW5zZXJ0aW9ucygr KQo+IGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2FkYy9yb2NrY2hpcC1zYXJhZGMuYwo+Cj4g ZGlmZiAtLWdpdCBhL2RyaXZlcnMvYWRjL0tjb25maWcgYi9kcml2ZXJzL2FkYy9LY29uZmlnCj4g aW5kZXggZTUzMzVmNy4uODMwZmUwZiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2FkYy9LY29uZmln Cj4gKysrIGIvZHJpdmVycy9hZGMvS2NvbmZpZwo+IEBAIC0yMCw2ICsyMCwxNSBAQCBjb25maWcg QURDX0VYWU5PUwo+IAkgIC0gMTItYml0IHJlc29sdXRpb24KPiAJICAtIDYwMCBLU1BTIG9mIHNh bXBsZSByYXRlCj4KPiArY29uZmlnIFNBUkFEQ19ST0NLQ0hJUAo+ICsJYm9vbCAiRW5hYmxlIFJv Y2tjaGlwIFNBUkFEQyBkcml2ZXIiCj4gKwloZWxwCj4gKwkgIFRoaXMgZW5hYmxlcyBkcml2ZXIg Zm9yIFJvY2tjaGlwIFNBUkFEQy4KPiArCSAgSXQgcHJvdmlkZXM6Cj4gKwkgIC0gMn42IGFuYWxv ZyBpbnB1dCBjaGFubmVscwo+ICsJICAtIDFPLWJpdCByZXNvbHV0aW9uCj4gKwkgIC0gMU1TUFMg b2Ygc2FtcGxlIHJhdGUKPiArCj4gY29uZmlnIEFEQ19TQU5EQk9YCj4gCWJvb2wgIkVuYWJsZSBT YW5kYm94IEFEQyB0ZXN0IGRyaXZlciIKPiAJaGVscAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Fk Yy9NYWtlZmlsZSBiL2RyaXZlcnMvYWRjL01ha2VmaWxlCj4gaW5kZXggY2ViZjI2ZC4uNGI1YWE2 OSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2FkYy9NYWtlZmlsZQo+ICsrKyBiL2RyaXZlcnMvYWRj L01ha2VmaWxlCj4gQEAgLTgsMyArOCw0IEBACj4gb2JqLSQoQ09ORklHX0FEQykgKz0gYWRjLXVj bGFzcy5vCj4gb2JqLSQoQ09ORklHX0FEQ19FWFlOT1MpICs9IGV4eW5vcy1hZGMubwo+IG9iai0k KENPTkZJR19BRENfU0FOREJPWCkgKz0gc2FuZGJveC5vCj4gK29iai0kKENPTkZJR19TQVJBRENf Uk9DS0NISVApICs9IHJvY2tjaGlwLXNhcmFkYy5vCgpEbyB5b3UgZmVlbCBzdHJvbmdseSBhYm91 dCB0aGUgIlNBUkFEQ19ST0NLQ0hJUCIgb3Igd291bGQgIkFEQ19ST0NLQ0hJUCIgCmJlIGNvcnJl Y3QgYXMgd2VsbD8gIEkgZG9uJ3QgY2FyZSBlaXRoZXIgd2F5LCBidXQgdGhpcyBpcyB0aGUgZmly c3QgZW50cnkgCmhlcmUgdGhhdCBkb2VzIG5vdCBzdGFydCB3aXRoIENPTkZJR19BRENfLCBzbyBJ IGFtIHdvbmRlcmluZy4uLgoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9hZGMvcm9ja2NoaXAtc2Fy YWRjLmMgYi9kcml2ZXJzL2FkYy9yb2NrY2hpcC1zYXJhZGMuYwo+IG5ldyBmaWxlIG1vZGUgMTAw NjQ0Cj4gaW5kZXggMDAwMDAwMC4uNWM3YzNkOQo+IC0tLSAvZGV2L251bGwKPiArKysgYi9kcml2 ZXJzL2FkYy9yb2NrY2hpcC1zYXJhZGMuYwo+IEBAIC0wLDAgKzEsMTg4IEBACj4gKy8qCj4gKyAq IChDKSBDb3B5cmlnaHQgMjAxNywgRnV6aG91IFJvY2tjaGlwIEVsZWN0cm9uaWNzIENvLiwgTHRk Cj4gKyAqCj4gKyAqIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOglHUEwtMi4wKwo+ICsgKgo+ICsg KiBSb2NrY2hpcCBTYXJhZGMgZHJpdmVyIGZvciBVLUJvb3QKClNob3VsZCB0aGlzIGJlIFNBUkFE QyAoYWxsIHVwcGVyY2FzZSk/Cgo+ICsgKi8KPiArCj4gKyNpbmNsdWRlIDxhc20vaW8uaD4KPiAr I2luY2x1ZGUgPGNsay5oPgo+ICsjaW5jbHVkZSA8Y29tbW9uLmg+Cj4gKyNpbmNsdWRlIDxkbS5o Pgo+ICsjaW5jbHVkZSA8ZXJybm8uaD4KPiArI2luY2x1ZGUgPGFkYy5oPgoKUGxlYXNlIHNlZSBo dHRwczovL3d3dy5kZW54LmRlL3dpa2kvVS1Cb290L0NvZGluZ1N0eWxlIGZvciB0aGUgaW5jbHVk ZSAKb3JkZXIuIFBsZWFzZSByZXZpc2UuCgpAU2ltb246IHllcywgSSBhbSBxdWljayBzdHVkeSA7 LSkKCj4gKwo+ICsjZGVmaW5lIFNBUkFEQ19EQVRBCQkJMHgwMAo+ICsKPiArI2RlZmluZSBTQVJB RENfU1RBUwkJCTB4MDQKClBsZWFzZSBzZWUgaHR0cHM6Ly93d3cuZGVueC5kZS93aWtpL1UtQm9v dC9Db2RpbmdTdHlsZSBmb3IgdGhlIGd1aWRlbGluZXMgCm9uIHVzaW5nIHN0cnVjdHVyZXMgZm9y IEkvTyBhY2Nlc3Nlcy4gIFBsZWFzZSByZXZpc2UuCgo+ICsjZGVmaW5lIFNBUkFEQ19TVEFTX0JV U1kJCUJJVCgwKQo+ICsKPiArI2RlZmluZSBTQVJBRENfQ1RSTAkJCTB4MDgKPiArI2RlZmluZSBT QVJBRENfQ1RSTF9QT1dFUl9DVFJMCQlCSVQoMykKPiArI2RlZmluZSBTQVJBRENfQ1RSTF9DSE5f TUFTSwkJMHg3Cj4gKyNkZWZpbmUgU0FSQURDX0NUUkxfSVJRX1NUQVRVUwkJQklUKDYpCj4gKyNk ZWZpbmUgU0FSQURDX0NUUkxfSVJRX0VOQUJMRQkJQklUKDUpCj4gKwo+ICsjZGVmaW5lIFNBUkFE Q19ETFlfUFVfU09DCQkweDBjCj4gKwo+ICsjZGVmaW5lIFNBUkFEQ19USU1FT1VUCQkJKDEwMCAq IDEwMDApCj4gKwo+ICtzdHJ1Y3Qgcm9ja2NoaXBfc2FyYWRjX2RhdGEgewo+ICsJaW50CQkJCW51 bV9iaXRzOwo+ICsJaW50CQkJCW51bV9jaGFubmVsczsKPiArCXVuc2lnbmVkIGxvbmcJCQljbGtf cmF0ZTsKPiArfTsKPiArCj4gK3N0cnVjdCByb2NrY2hpcF9zYXJhZGNfcHJpdiB7Cj4gKwlmZHRf YWRkcl90CQkJCXJlZ3M7Cj4gKwlpbnQgCQkJCQlhY3RpdmVfY2hhbm5lbDsKPiArCWNvbnN0IHN0 cnVjdCByb2NrY2hpcF9zYXJhZGNfZGF0YQkqZGF0YTsKPiArfTsKPiArCj4gK2ludCByb2NrY2hp cF9zYXJhZGNfY2hhbm5lbF9kYXRhKHN0cnVjdCB1ZGV2aWNlICpkZXYsIGludCBjaGFubmVsLAo+ ICsJCQkgICAgdW5zaWduZWQgaW50ICpkYXRhKQo+ICt7Cj4gKwlzdHJ1Y3Qgcm9ja2NoaXBfc2Fy YWRjX3ByaXYgKnByaXYgPSBkZXZfZ2V0X3ByaXYoZGV2KTsKPiArCj4gKwlpZiAoY2hhbm5lbCAh PSBwcml2LT5hY3RpdmVfY2hhbm5lbCkgewo+ICsJCWVycm9yKCJSZXF1ZXN0ZWQgY2hhbm5lbCBp cyBub3QgYWN0aXZlISIpOwo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsJfQo+ICsKPiArCWlmICgo cmVhZGwocHJpdi0+cmVncyArIFNBUkFEQ19DVFJMKSAmIFNBUkFEQ19DVFJMX0lSUV9TVEFUVVMp ICE9IFNBUkFEQ19DVFJMX0lSUV9TVEFUVVMpCj4gKwkJcmV0dXJuIC1FQlVTWTsKPiArCj4gKwkv KiBSZWFkIHZhbHVlICovCj4gKwkqZGF0YSA9IHJlYWRsKHByaXYtPnJlZ3MgKyBTQVJBRENfREFU QSk7Cj4gKwkqZGF0YSAmPSAoMSA8PCBwcml2LT5kYXRhLT5udW1fYml0cykgLSAxOwoKVGhpcyBy ZWNvbXB1dGVzIHRoZSBkYXRhX21hc2sgKGZyb20gYmVsb3cpLgpDYW4gd2UganVzdCB1c2UgdGhl IGRhdGFfbWFzayBhZ2Fpbj8KCj4gKwo+ICsJLyogUG93ZXIgZG93biBhZGMgKi8KPiArCXdyaXRl bCgwLCBwcml2LT5yZWdzICsgU0FSQURDX0NUUkwpOwo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4g Kwo+ICtpbnQgcm9ja2NoaXBfc2FyYWRjX3N0YXJ0X2NoYW5uZWwoc3RydWN0IHVkZXZpY2UgKmRl diwgaW50IGNoYW5uZWwpCj4gK3sKPiArCXN0cnVjdCByb2NrY2hpcF9zYXJhZGNfcHJpdiAqcHJp diA9IGRldl9nZXRfcHJpdihkZXYpOwo+ICsKPiArCWlmIChjaGFubmVsIDwgMCB8fCBjaGFubmVs ID49IHByaXYtPmRhdGEtPm51bV9jaGFubmVscykgewo+ICsJCWVycm9yKCJSZXF1ZXN0ZWQgY2hh bm5lbCBpcyBpbnZhbGlkISIpOwo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsJfQo+ICsKPiArCS8q IDggY2xvY2sgcGVyaW9kcyBhcyBkZWxheSBiZXR3ZWVuIHBvd2VyIHVwIGFuZCBzdGFydCBjbWQg Ki8KPiArCXdyaXRlbCg4LCBwcml2LT5yZWdzICsgU0FSQURDX0RMWV9QVV9TT0MpOwo+ICsKPiAr CS8qIFNlbGVjdCB0aGUgY2hhbm5lbCB0byBiZSB1c2VkIGFuZCB0cmlnZ2VyIGNvbnZlcnNpb24g Ki8KPiArCXdyaXRlbChTQVJBRENfQ1RSTF9QT1dFUl9DVFJMCj4gKwkJCXwgKGNoYW5uZWwgJiBT QVJBRENfQ1RSTF9DSE5fTUFTSykgfCBTQVJBRENfQ1RSTF9JUlFfRU5BQkxFLAoKVGhpcyBsaW5l IGRvZXMgbm90IG1hdGNoIHRoZSBzdHlsZSBndWlkZWxpbmU6IGl0IGlzIHRvbyB3aWRlIGFuZCB0 aGUgCm9wZXJhdG9yIHNob3VsZCBiZSBiZWZvcmUgdGhlIGxpbmUtYnJlYWsuCgpEaWQgeW91IHJ1 biBjaGVja3BhdGNoIG9yIHVzZSBwYXRtYW4/Cgo+ICsJCSAgIHByaXYtPnJlZ3MgKyBTQVJBRENf Q1RSTCk7Cj4gKwo+ICsJcHJpdi0+YWN0aXZlX2NoYW5uZWwgPSBjaGFubmVsOwo+ICsKPiArCXJl dHVybiAwOwo+ICt9Cj4gKwo+ICtpbnQgcm9ja2NoaXBfc2FyYWRjX3N0b3Aoc3RydWN0IHVkZXZp Y2UgKmRldikKPiArewo+ICsJc3RydWN0IHJvY2tjaGlwX3NhcmFkY19wcml2ICpwcml2ID0gZGV2 X2dldF9wcml2KGRldik7Cj4gKwo+ICsJLyogUG93ZXIgZG93biBhZGMgKi8KPiArCXdyaXRlbCgw LCBwcml2LT5yZWdzICsgU0FSQURDX0NUUkwpOwo+ICsKPiArCXByaXYtPmFjdGl2ZV9jaGFubmVs ID0gLTE7Cj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gK2ludCByb2NrY2hpcF9zYXJhZGNf cHJvYmUoc3RydWN0IHVkZXZpY2UgKmRldikKPiArewo+ICsJc3RydWN0IHJvY2tjaGlwX3NhcmFk Y19wcml2ICpwcml2ID0gZGV2X2dldF9wcml2KGRldik7Cj4gKwlzdHJ1Y3QgY2xrIGNsazsKPiAr CWludCByZXQ7Cj4gKwo+ICsJcmV0ID0gY2xrX2dldF9ieV9pbmRleChkZXYsIDAsICZjbGspOwo+ ICsJaWYgKHJldCkKPiArCQlyZXR1cm4gcmV0Owo+ICsKPiArCXJldCA9IGNsa19zZXRfcmF0ZSgm Y2xrLCBwcml2LT5kYXRhLT5jbGtfcmF0ZSk7Cj4gKwlpZiAoSVNfRVJSX1ZBTFVFKHJldCkpCj4g KwkJcmV0dXJuIHJldDsKPiArCj4gKwlwcml2LT5hY3RpdmVfY2hhbm5lbCA9IC0xOwo+ICsKPiAr CXJldHVybiAwOwo+ICt9Cj4gKwo+ICtpbnQgcm9ja2NoaXBfc2FyYWRjX29mZGF0YV90b19wbGF0 ZGF0YShzdHJ1Y3QgdWRldmljZSAqZGV2KQo+ICt7Cj4gKwlzdHJ1Y3QgYWRjX3VjbGFzc19wbGF0 ZGF0YSAqdWNfcGRhdGEgPSBkZXZfZ2V0X3VjbGFzc19wbGF0ZGF0YShkZXYpOwo+ICsJc3RydWN0 IHJvY2tjaGlwX3NhcmFkY19wcml2ICpwcml2ID0gZGV2X2dldF9wcml2KGRldik7Cj4gKwlzdHJ1 Y3Qgcm9ja2NoaXBfc2FyYWRjX2RhdGEgKmRhdGEgPQo+ICsJCQkJCShzdHJ1Y3Qgcm9ja2NoaXBf c2FyYWRjX2RhdGEgKilkZXZfZ2V0X2RyaXZlcl9kYXRhKGRldik7Cj4gKwo+ICsJcHJpdi0+cmVn cyA9IGRldmZkdF9nZXRfYWRkcihkZXYpOwoKU2hvdWxkbid0IHRoaXMgYmUgZGV2X3JlYWRfYWRk cj8KCj4gKwlpZiAocHJpdi0+cmVncyA9PSBGRFRfQUREUl9UX05PTkUpIHsKPiArCQllcnJvcigi RGV2OiAlcyAtIGNhbid0IGdldCBhZGRyZXNzISIsIGRldi0+bmFtZSk7Cj4gKwkJcmV0dXJuIC1F Tk9EQVRBOwo+ICsJfQo+ICsKPiArCXByaXYtPmRhdGEgPSBkYXRhOwo+ICsJdWNfcGRhdGEtPmRh dGFfbWFzayA9ICgxIDw8IHByaXYtPmRhdGEtPm51bV9iaXRzKSAtIDE7Owo+ICsJdWNfcGRhdGEt PmRhdGFfZm9ybWF0ID0gQURDX0RBVEFfRk9STUFUX0JJTjsKPiArCXVjX3BkYXRhLT5kYXRhX3Rp bWVvdXRfdXMgPSBTQVJBRENfVElNRU9VVCAvIDU7Cj4gKwl1Y19wZGF0YS0+Y2hhbm5lbF9tYXNr ID0gKDEgPDwgcHJpdi0+ZGF0YS0+bnVtX2NoYW5uZWxzKSAtIDE7Cj4gKwo+ICsJcmV0dXJuIDA7 Cj4gK30KPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgYWRjX29wcyByb2NrY2hpcF9zYXJhZGNf b3BzID0gewo+ICsJLnN0YXJ0X2NoYW5uZWwgPSByb2NrY2hpcF9zYXJhZGNfc3RhcnRfY2hhbm5l bCwKPiArCS5jaGFubmVsX2RhdGEgPSByb2NrY2hpcF9zYXJhZGNfY2hhbm5lbF9kYXRhLAo+ICsJ LnN0b3AgPSByb2NrY2hpcF9zYXJhZGNfc3RvcCwKPiArfTsKPiArCj4gK3N0YXRpYyBjb25zdCBz dHJ1Y3Qgcm9ja2NoaXBfc2FyYWRjX2RhdGEgc2FyYWRjX2RhdGEgPSB7Cj4gKwkubnVtX2JpdHMg PSAxMCwKPiArCS5udW1fY2hhbm5lbHMgPSAzLAo+ICsJLmNsa19yYXRlID0gMTAwMDAwMCwKPiAr fTsKPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgcm9ja2NoaXBfc2FyYWRjX2RhdGEgcmszMDY2 X3RzYWRjX2RhdGEgPSB7Cj4gKwkubnVtX2JpdHMgPSAxMiwKPiArCS5udW1fY2hhbm5lbHMgPSAy LAo+ICsJLmNsa19yYXRlID0gNTAwMDAsCj4gK307Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0 IHJvY2tjaGlwX3NhcmFkY19kYXRhIHJrMzM5OV9zYXJhZGNfZGF0YSA9IHsKPiArCS5udW1fYml0 cyA9IDEwLAo+ICsJLm51bV9jaGFubmVscyA9IDYsCj4gKwkuY2xrX3JhdGUgPSAxMDAwMDAwLAo+ ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCB1ZGV2aWNlX2lkIHJvY2tjaGlwX3NhcmFk Y19pZHNbXSA9IHsKPiArCXsKPiArCQkuY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxzYXJhZGMiLAo+ ICsJCS5kYXRhID0gKHVsb25nKSZzYXJhZGNfZGF0YSwKPiArCX0sCj4gKwl7Cj4gKwkJLmNvbXBh dGlibGUgPSAicm9ja2NoaXAscmszMDY2LXRzYWRjIiwKPiArCQkuZGF0YSA9ICh1bG9uZykmcmsz MDY2X3RzYWRjX2RhdGEsCj4gKwl9LCB7Cj4gKwkJLmNvbXBhdGlibGUgPSAicm9ja2NoaXAscmsz Mzk5LXNhcmFkYyIsCj4gKwkJLmRhdGEgPSAodWxvbmcpJnJrMzM5OV9zYXJhZGNfZGF0YSwKPiAr CX0sCj4gKwl7IH0KPiArfTsKPiArCj4gK1VfQk9PVF9EUklWRVIocm9ja2NoaXBfc2FyYWRjKSA9 IHsKPiArCS5uYW1lCQk9ICJyb2NrY2hpcF9zYXJhZGMiLAo+ICsJLmlkCQk9IFVDTEFTU19BREMs Cj4gKwkub2ZfbWF0Y2gJPSByb2NrY2hpcF9zYXJhZGNfaWRzLAo+ICsJLm9wcwkJPSAmcm9ja2No aXBfc2FyYWRjX29wcywKPiArCS5wcm9iZQkJPSByb2NrY2hpcF9zYXJhZGNfcHJvYmUsCj4gKwku b2ZkYXRhX3RvX3BsYXRkYXRhID0gcm9ja2NoaXBfc2FyYWRjX29mZGF0YV90b19wbGF0ZGF0YSwK PiArCS5wcml2X2F1dG9fYWxsb2Nfc2l6ZSA9IHNpemVvZihzdHJ1Y3Qgcm9ja2NoaXBfc2FyYWRj X3ByaXYpLAo+ICt9Owo+Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fClUtQm9vdCBtYWlsaW5nIGxpc3QKVS1Cb290QGxpc3RzLmRlbnguZGUKaHR0cHM6Ly9s aXN0cy5kZW54LmRlL2xpc3RpbmZvL3UtYm9vdAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Tomsich Date: Wed, 13 Sep 2017 22:40:27 +0200 (CEST) Subject: [U-Boot] [U-Boot,1/8] adc: Add driver for Rockchip Saradc In-Reply-To: <1505297379-12638-2-git-send-email-david.wu@rock-chips.com> References: <1505297379-12638-2-git-send-email-david.wu@rock-chips.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, 13 Sep 2017, David Wu wrote: > The ADC can support some channels signal-ended some bits Successive Approximation > Register (SAR) A/D Converter, like 6-channel and 10-bit. It converts the analog > input signal into some bits binary digital codes. > > Signed-off-by: David Wu Reviewed-by: Philipp Tomsich Please see below for requested changes. > --- > drivers/adc/Kconfig | 9 ++ > drivers/adc/Makefile | 1 + > drivers/adc/rockchip-saradc.c | 188 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 198 insertions(+) > create mode 100644 drivers/adc/rockchip-saradc.c > > diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig > index e5335f7..830fe0f 100644 > --- a/drivers/adc/Kconfig > +++ b/drivers/adc/Kconfig > @@ -20,6 +20,15 @@ config ADC_EXYNOS > - 12-bit resolution > - 600 KSPS of sample rate > > +config SARADC_ROCKCHIP > + bool "Enable Rockchip SARADC driver" > + help > + This enables driver for Rockchip SARADC. > + It provides: > + - 2~6 analog input channels > + - 1O-bit resolution > + - 1MSPS of sample rate > + > config ADC_SANDBOX > bool "Enable Sandbox ADC test driver" > help > diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile > index cebf26d..4b5aa69 100644 > --- a/drivers/adc/Makefile > +++ b/drivers/adc/Makefile > @@ -8,3 +8,4 @@ > obj-$(CONFIG_ADC) += adc-uclass.o > obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o > obj-$(CONFIG_ADC_SANDBOX) += sandbox.o > +obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o Do you feel strongly about the "SARADC_ROCKCHIP" or would "ADC_ROCKCHIP" be correct as well? I don't care either way, but this is the first entry here that does not start with CONFIG_ADC_, so I am wondering... > diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c > new file mode 100644 > index 0000000..5c7c3d9 > --- /dev/null > +++ b/drivers/adc/rockchip-saradc.c > @@ -0,0 +1,188 @@ > +/* > + * (C) Copyright 2017, Fuzhou Rockchip Electronics Co., Ltd > + * > + * SPDX-License-Identifier: GPL-2.0+ > + * > + * Rockchip Saradc driver for U-Boot Should this be SARADC (all uppercase)? > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include Please see https://www.denx.de/wiki/U-Boot/CodingStyle for the include order. Please revise. @Simon: yes, I am quick study ;-) > + > +#define SARADC_DATA 0x00 > + > +#define SARADC_STAS 0x04 Please see https://www.denx.de/wiki/U-Boot/CodingStyle for the guidelines on using structures for I/O accesses. Please revise. > +#define SARADC_STAS_BUSY BIT(0) > + > +#define SARADC_CTRL 0x08 > +#define SARADC_CTRL_POWER_CTRL BIT(3) > +#define SARADC_CTRL_CHN_MASK 0x7 > +#define SARADC_CTRL_IRQ_STATUS BIT(6) > +#define SARADC_CTRL_IRQ_ENABLE BIT(5) > + > +#define SARADC_DLY_PU_SOC 0x0c > + > +#define SARADC_TIMEOUT (100 * 1000) > + > +struct rockchip_saradc_data { > + int num_bits; > + int num_channels; > + unsigned long clk_rate; > +}; > + > +struct rockchip_saradc_priv { > + fdt_addr_t regs; > + int active_channel; > + const struct rockchip_saradc_data *data; > +}; > + > +int rockchip_saradc_channel_data(struct udevice *dev, int channel, > + unsigned int *data) > +{ > + struct rockchip_saradc_priv *priv = dev_get_priv(dev); > + > + if (channel != priv->active_channel) { > + error("Requested channel is not active!"); > + return -EINVAL; > + } > + > + if ((readl(priv->regs + SARADC_CTRL) & SARADC_CTRL_IRQ_STATUS) != SARADC_CTRL_IRQ_STATUS) > + return -EBUSY; > + > + /* Read value */ > + *data = readl(priv->regs + SARADC_DATA); > + *data &= (1 << priv->data->num_bits) - 1; This recomputes the data_mask (from below). Can we just use the data_mask again? > + > + /* Power down adc */ > + writel(0, priv->regs + SARADC_CTRL); > + > + return 0; > +} > + > +int rockchip_saradc_start_channel(struct udevice *dev, int channel) > +{ > + struct rockchip_saradc_priv *priv = dev_get_priv(dev); > + > + if (channel < 0 || channel >= priv->data->num_channels) { > + error("Requested channel is invalid!"); > + return -EINVAL; > + } > + > + /* 8 clock periods as delay between power up and start cmd */ > + writel(8, priv->regs + SARADC_DLY_PU_SOC); > + > + /* Select the channel to be used and trigger conversion */ > + writel(SARADC_CTRL_POWER_CTRL > + | (channel & SARADC_CTRL_CHN_MASK) | SARADC_CTRL_IRQ_ENABLE, This line does not match the style guideline: it is too wide and the operator should be before the line-break. Did you run checkpatch or use patman? > + priv->regs + SARADC_CTRL); > + > + priv->active_channel = channel; > + > + return 0; > +} > + > +int rockchip_saradc_stop(struct udevice *dev) > +{ > + struct rockchip_saradc_priv *priv = dev_get_priv(dev); > + > + /* Power down adc */ > + writel(0, priv->regs + SARADC_CTRL); > + > + priv->active_channel = -1; > + > + return 0; > +} > + > +int rockchip_saradc_probe(struct udevice *dev) > +{ > + struct rockchip_saradc_priv *priv = dev_get_priv(dev); > + struct clk clk; > + int ret; > + > + ret = clk_get_by_index(dev, 0, &clk); > + if (ret) > + return ret; > + > + ret = clk_set_rate(&clk, priv->data->clk_rate); > + if (IS_ERR_VALUE(ret)) > + return ret; > + > + priv->active_channel = -1; > + > + return 0; > +} > + > +int rockchip_saradc_ofdata_to_platdata(struct udevice *dev) > +{ > + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); > + struct rockchip_saradc_priv *priv = dev_get_priv(dev); > + struct rockchip_saradc_data *data = > + (struct rockchip_saradc_data *)dev_get_driver_data(dev); > + > + priv->regs = devfdt_get_addr(dev); Shouldn't this be dev_read_addr? > + if (priv->regs == FDT_ADDR_T_NONE) { > + error("Dev: %s - can't get address!", dev->name); > + return -ENODATA; > + } > + > + priv->data = data; > + uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;; > + uc_pdata->data_format = ADC_DATA_FORMAT_BIN; > + uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; > + uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; > + > + return 0; > +} > + > +static const struct adc_ops rockchip_saradc_ops = { > + .start_channel = rockchip_saradc_start_channel, > + .channel_data = rockchip_saradc_channel_data, > + .stop = rockchip_saradc_stop, > +}; > + > +static const struct rockchip_saradc_data saradc_data = { > + .num_bits = 10, > + .num_channels = 3, > + .clk_rate = 1000000, > +}; > + > +static const struct rockchip_saradc_data rk3066_tsadc_data = { > + .num_bits = 12, > + .num_channels = 2, > + .clk_rate = 50000, > +}; > + > +static const struct rockchip_saradc_data rk3399_saradc_data = { > + .num_bits = 10, > + .num_channels = 6, > + .clk_rate = 1000000, > +}; > + > +static const struct udevice_id rockchip_saradc_ids[] = { > + { > + .compatible = "rockchip,saradc", > + .data = (ulong)&saradc_data, > + }, > + { > + .compatible = "rockchip,rk3066-tsadc", > + .data = (ulong)&rk3066_tsadc_data, > + }, { > + .compatible = "rockchip,rk3399-saradc", > + .data = (ulong)&rk3399_saradc_data, > + }, > + { } > +}; > + > +U_BOOT_DRIVER(rockchip_saradc) = { > + .name = "rockchip_saradc", > + .id = UCLASS_ADC, > + .of_match = rockchip_saradc_ids, > + .ops = &rockchip_saradc_ops, > + .probe = rockchip_saradc_probe, > + .ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata, > + .priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv), > +}; >