From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Tomsich Subject: Re: [U-Boot, 3/8] clk: rockchip: Add rv1108 Saradc clock support Date: Wed, 13 Sep 2017 22:45:37 +0200 (CEST) Message-ID: References: <1505297379-12638-4-git-send-email-david.wu@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1505297379-12638-4-git-send-email-david.wu@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To: David Wu Cc: huangtao@rock-chips.com, linux-rockchip@lists.infradead.org, zhangqing@rock-chips.com, u-boot@lists.denx.de, p.marczak@samsung.com, andy.yan@rock-chips.com, chenjh@rock-chips.com List-Id: linux-rockchip.vger.kernel.org CgpPbiBXZWQsIDEzIFNlcCAyMDE3LCBEYXZpZCBXdSB3cm90ZToKCj4gU2lnbmVkLW9mZi1ieTog RGF2aWQgV3UgPGRhdmlkLnd1QHJvY2stY2hpcHMuY29tPgoKUmV2aWV3ZWQtYnk6IFBoaWxpcHAg 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Philipp Tomsich Date: Wed, 13 Sep 2017 22:45:37 +0200 (CEST) Subject: [U-Boot] [U-Boot, 3/8] clk: rockchip: Add rv1108 Saradc clock support In-Reply-To: <1505297379-12638-4-git-send-email-david.wu@rock-chips.com> References: <1505297379-12638-4-git-send-email-david.wu@rock-chips.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, 13 Sep 2017, David Wu wrote: > Signed-off-by: David Wu Reviewed-by: Philipp Tomsich > --- > arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5 ++++ > drivers/clk/rockchip/clk_rv1108.c | 35 +++++++++++++++++++++++++ > include/dt-bindings/clock/rv1108-cru.h | 2 ++ > 3 files changed, 42 insertions(+) > > diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h > index 2a1ae69..b134559 100644 > --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h > +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h > @@ -90,6 +90,11 @@ enum { > CORE_CLK_DIV_SHIFT = 0, > CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, > > + /* CLKSEL_CON22 */ > + CLK_SARADC_DIV_CON_SHIFT= 0, > + CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT, Can we use GENMASK here? > + CLK_SARADC_DIV_CON_WIDTH= 10, > + > /* CLKSEL24_CON */ > MAC_PLL_SEL_SHIFT = 12, > MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, > diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c > index cf966bb..aa989c6 100644 > --- a/drivers/clk/rockchip/clk_rv1108.c > +++ b/drivers/clk/rockchip/clk_rv1108.c > @@ -36,6 +36,11 @@ enum { > #hz "Hz cannot be hit with PLL "\ > "divisors on line " __stringify(__LINE__)); > > +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift) > +{ > + return (val >> shift) & ((1 << width) - 1); The comment regarding bitfield.h applies again. > +} > + > /* use interge mode*/ typo: integer > static inline int rv1108_pll_id(enum rk_clk_id clk_id) > { > @@ -130,6 +135,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) > return DIV_TO_RATE(pll_rate, div); > } > > +static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru) > +{ > + u32 div, val; > + > + val = readl(&cru->clksel_con[22]); > + div = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH, > + CLK_SARADC_DIV_CON_SHIFT); > + > + return DIV_TO_RATE(OSC_HZ, div); > +} > + > +static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) > +{ > + int src_clk_div; > + > + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; > + assert(src_clk_div < 128); > + > + rk_clrsetreg(&cru->clksel_con[22], > + CLK_SARADC_DIV_CON_MASK, > + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); > + > + return rv1108_saradc_get_clk(cru); > +} > + > static ulong rv1108_clk_get_rate(struct clk *clk) > { > struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); > @@ -137,6 +167,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk) > switch (clk->id) { > case 0 ... 63: > return rkclk_pll_get_rate(priv->cru, clk->id); > + case SCLK_SARADC: > + return rv1108_saradc_get_clk(priv->cru); > default: > return -ENOENT; > } > @@ -154,6 +186,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) > case SCLK_SFC: > new_rate = rv1108_sfc_set_clk(priv->cru, rate); > break; > + case SCLK_SARADC: > + new_rate = rv1108_saradc_set_clk(priv->cru, rate); > + break; > default: > return -ENOENT; > } > diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h > index d2ad3bb..7defc6b 100644 > --- a/include/dt-bindings/clock/rv1108-cru.h > +++ b/include/dt-bindings/clock/rv1108-cru.h > @@ -39,6 +39,7 @@ > #define SCLK_MAC_TX 88 > #define SCLK_MACREF 89 > #define SCLK_MACREF_OUT 90 > +#define SCLK_SARADC 91 > > > /* aclk gates */ > @@ -67,6 +68,7 @@ > #define PCLK_TIMER 270 > #define PCLK_PERI 271 > #define PCLK_GMAC 272 > +#define PCLK_SARADC 273 > > /* hclk gates */ > #define HCLK_I2S0_8CH 320 >