* [U-Boot] [PATCH v2 0/7] rockchip: add new SoC support for RK3128
@ 2017-11-27 9:51 Kever Yang
2017-11-27 9:51 ` [U-Boot] [PATCH v2 1/7] rockchip: rk3128: add device tree file Kever Yang
` (6 more replies)
0 siblings, 7 replies; 21+ messages in thread
From: Kever Yang @ 2017-11-27 9:51 UTC (permalink / raw)
To: u-boot
RK3128 is a quad-core ARM Cortex-A7 SoC, this patch set add basic
support for it, it does not support SPL/TPL now, and the sdram driver
only support get dram size from sysreg in U-Boot stage. Most of basic
driver like clock, pinctrl, sysreset have been implement, and more
drivers like mac and display will be later.
Changes in v2:
- update setup_boot_mode() with master
- enable board_late_init()
- add clock for saradc, vop, nandc, i2c
- update driver bind for sysreset driver and reset driver
- add "rockchip,rk3126-cru" for compatible
- remove debug info
- update GPIO2C4/C5 SHIFT
- enable usb nodes
Kever Yang (7):
rockchip: rk3128: add device tree file
rockchip: rk3128: add soc basic support
rockchip: rk3128: add clock driver
rockchip: rk3128: add pinctrl driver
rockchip: rk3128: add evb-rk3128 support
rockchip: rk3128: add defconfig for evb-rk3128
rockchip: rk3128: add sdram driver
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3128-evb.dts | 95 +++
arch/arm/dts/rk3128.dtsi | 804 ++++++++++++++++++++++++
arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 212 +++++++
arch/arm/include/asm/arch-rockchip/grf_rk3128.h | 551 ++++++++++++++++
arch/arm/mach-rockchip/Kconfig | 10 +
arch/arm/mach-rockchip/Makefile | 2 +
arch/arm/mach-rockchip/rk3128-board.c | 127 ++++
arch/arm/mach-rockchip/rk3128/Kconfig | 24 +
arch/arm/mach-rockchip/rk3128/Makefile | 9 +
arch/arm/mach-rockchip/rk3128/clk_rk3128.c | 32 +
arch/arm/mach-rockchip/rk3128/rk3128.c | 12 +
arch/arm/mach-rockchip/rk3128/syscon_rk3128.c | 21 +
board/rockchip/evb_rk3128/Kconfig | 15 +
board/rockchip/evb_rk3128/MAINTAINERS | 6 +
board/rockchip/evb_rk3128/Makefile | 7 +
board/rockchip/evb_rk3128/evb-rk3128.c | 9 +
configs/evb-rk3128_defconfig | 56 ++
drivers/clk/rockchip/Makefile | 3 +-
drivers/clk/rockchip/clk_rk3128.c | 609 ++++++++++++++++++
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/rockchip/Makefile | 4 +-
drivers/pinctrl/rockchip/pinctrl_rk3128.c | 187 ++++++
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3128.c | 59 ++
include/configs/evb_rk3128.h | 15 +
include/configs/rk3128_common.h | 70 +++
include/dt-bindings/clock/rk3128-cru.h | 190 ++++++
28 files changed, 3138 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/dts/rk3128-evb.dts
create mode 100644 arch/arm/dts/rk3128.dtsi
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3128.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3128.h
create mode 100644 arch/arm/mach-rockchip/rk3128-board.c
create mode 100644 arch/arm/mach-rockchip/rk3128/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3128/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3128/clk_rk3128.c
create mode 100644 arch/arm/mach-rockchip/rk3128/rk3128.c
create mode 100644 arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
create mode 100644 board/rockchip/evb_rk3128/Kconfig
create mode 100644 board/rockchip/evb_rk3128/MAINTAINERS
create mode 100644 board/rockchip/evb_rk3128/Makefile
create mode 100644 board/rockchip/evb_rk3128/evb-rk3128.c
create mode 100644 configs/evb-rk3128_defconfig
create mode 100644 drivers/clk/rockchip/clk_rk3128.c
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c
create mode 100644 drivers/ram/rockchip/sdram_rk3128.c
create mode 100644 include/configs/evb_rk3128.h
create mode 100644 include/configs/rk3128_common.h
create mode 100644 include/dt-bindings/clock/rk3128-cru.h
--
1.9.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 1/7] rockchip: rk3128: add device tree file
2017-11-27 9:51 [U-Boot] [PATCH v2 0/7] rockchip: add new SoC support for RK3128 Kever Yang
@ 2017-11-27 9:51 ` Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 2/7] rockchip: rk3128: add soc basic support Kever Yang
` (5 subsequent siblings)
6 siblings, 2 replies; 21+ messages in thread
From: Kever Yang @ 2017-11-27 9:51 UTC (permalink / raw)
To: u-boot
Add dts binding header for rk3128, files origin from kernel.
Series-Changes: 2
- fix i2c address
- add saradc and usb phy node
- emmc using fifo mode for there is no dma support in rk3128 emmc
- add some clock id in cru.h
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2: None
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3128-evb.dts | 95 ++++
arch/arm/dts/rk3128.dtsi | 804 +++++++++++++++++++++++++++++++++
include/dt-bindings/clock/rk3128-cru.h | 190 ++++++++
4 files changed, 1090 insertions(+)
create mode 100644 arch/arm/dts/rk3128-evb.dts
create mode 100644 arch/arm/dts/rk3128.dtsi
create mode 100644 include/dt-bindings/clock/rk3128-cru.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cd540e9..1b447a8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
+ rk3128-evb.dtb \
rk3188-radxarock.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts
new file mode 100644
index 0000000..6940af9
--- /dev/null
+++ b/arch/arm/dts/rk3128-evb.dts
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "rk3128.dtsi"
+
+/ {
+ model = "Rockchip RK3128 Evaluation board";
+ compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-drv {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_otg";
+ gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_host: vcc5v0-host-drv {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ hym8563: hym8563 at 51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci {
+ status = "okay";
+};
+
+&usb_otg {
+ vbus-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&emmc {
+ fifo-mode;
+ status = "okay";
+};
+
+&pinctrl {
+ usb_otg {
+ otg_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb_host {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
new file mode 100644
index 0000000..3ef2737
--- /dev/null
+++ b/arch/arm/dts/rk3128.dtsi
@@ -0,0 +1,804 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3128-cru.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "rockchip,rk3128";
+ rockchip,sram = <&sram>;
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ spi0 = &spi0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "rockchip,rk3128-smp";
+
+ cpu0:cpu at 0x000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x000>;
+ operating-points = <
+ /* KHz uV */
+ 816000 1000000
+ >;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu1:cpu at 0x001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x001>;
+ };
+
+ cpu2:cpu at 0x002 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x002>;
+ };
+
+ cpu3:cpu at 0x003 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x003>;
+ };
+ };
+
+ cpu_axi_bus: cpu_axi_bus {
+ compatible = "rockchip,cpu_axi_bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ qos {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ crypto {
+ reg = <0x10128080 0x20>;
+ };
+
+ core {
+ reg = <0x1012a000 0x20>;
+ };
+
+ peri {
+ reg = <0x1012c000 0x20>;
+ };
+
+ gpu {
+ reg = <0x1012d000 0x20>;
+ };
+
+ vpu {
+ reg = <0x1012e000 0x20>;
+ };
+
+ rga {
+ reg = <0x1012f000 0x20>;
+ };
+ ebc {
+ reg = <0x1012f080 0x20>;
+ };
+
+ iep {
+ reg = <0x1012f100 0x20>;
+ };
+
+ lcdc {
+ reg = <0x1012f180 0x20>;
+ rockchip,priority = <3 3>;
+ };
+
+ vip {
+ reg = <0x1012f200 0x20>;
+ rockchip,priority = <3 3>;
+ };
+ };
+
+ msch {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ msch at 10128000 {
+ reg = <0x10128000 0x20>;
+ rockchip,read-latency = <0x3f>;
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_suspend = <0x84000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ migrate = <0x84000005>;
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma: pdma at 20078000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x20078000 0x4000>;
+ arm,pl330-broken-no-flushp;//2
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ clocks = <&cru ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ xin12m: xin12m {
+ compatible = "fixed-clock";
+ clocks = <&xin24m>;
+ clock-frequency = <12000000>;
+ clock-output-names = "xin12m";
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ timer at 20044000 {
+ compatible = "arm,armv7-timer";
+ reg = <0x20044000 0xb8>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,broadcast = <1>;
+ };
+
+ watchdog: wdt at 2004c000 {
+ compatible = "rockchip,watch dog";
+ reg = <0x2004c000 0x100>;
+ clock-names = "pclk_wdt";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,irq = <1>;
+ rockchip,timeout = <60>;
+ rockchip,atboot = <1>;
+ rockchip,debug = <0>;
+ };
+
+ reset: reset at 20000110 {
+ compatible = "rockchip,reset";
+ reg = <0x20000110 0x24>;
+ #reset-cells = <1>;
+ };
+
+ nandc: nandc at 10500000 {
+ compatible = "rockchip,rk-nandc";
+ reg = <0x10500000 0x4000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
+ nandc_id = <0>;
+ clocks = <&cru SCLK_NANDC>,
+ <&cru HCLK_NANDC>,
+ <&cru SRST_NANDC>;
+ clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
+ };
+
+ dmc: dmc at 20004000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3128-dmc", "syscon";
+ reg = <0x0 0x20004000 0x0 0x1000>;
+ };
+
+ cru: clock-controller at 20000000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3128-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>;
+ assigned-clock-rates = <594000000>;
+ };
+
+ uart0: serial0 at 20060000 {
+ compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
+ reg = <0x20060000 0x100>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ dmas = <&pdma 2>, <&pdma 3>;
+ #dma-cells = <2>;
+ };
+
+ uart1: serial1 at 20064000 {
+ compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
+ reg = <0x20064000 0x100>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ dmas = <&pdma 4>, <&pdma 5>;
+ #dma-cells = <2>;
+ };
+
+ uart2: serial2 at 20068000 {
+ compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
+ reg = <0x20068000 0x100>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;
+ dmas = <&pdma 6>, <&pdma 7>;
+ #dma-cells = <2>;
+ };
+
+ saradc: saradc at 2006c000 {
+ compatible = "rockchip,saradc";
+ reg = <0x2006c000 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ pwm0: pwm0 at 20050000 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050000 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ };
+
+ pwm1: pwm1 at 20050010 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050010 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ };
+
+ pwm2: pwm2 at 20050020 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050020 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ };
+
+ pwm3: pwm3 at 20050030 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050030 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ };
+
+ sram: sram at 10080400 {
+ compatible = "rockchip,rk3128-smp-sram", "mmio-sram";
+ reg = <0x10080400 0x1C00>;
+ map-exec;
+ map-cacheable;
+ };
+
+ pmu: syscon at 100a0000 {
+ compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
+ reg = <0x100a0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ gic: interrupt-controller at 10139000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ reg = <0x10139000 0x1000>,
+ <0x1013a000 0x1000>,
+ <0x1013c000 0x2000>,
+ <0x1013e000 0x2000>;
+ interrupts = <GIC_PPI 9 0xf04>;
+ };
+
+ u2phy: usb2-phy {
+ compatible = "rockchip,rk3128-usb2phy";
+ reg = <0x017c 0x0c>;
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "usb480m_phy";
+ #phy-cells = <1>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+
+ usb_otg: usb at 10180000 {
+ compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
+ "snps,dwc2";
+ reg = <0x10180000 0x40000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ g-use-dma;
+ hnp-srp-disable;
+ phys = <&u2phy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ehci: usb at 101c0000 {
+ compatible = "generic-ehci";
+ reg = <0x101c0000 0x20000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2phy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb at 101e0000 {
+ compatible = "generic-ohci";
+ reg = <0x101e0000 0x20000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2phy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ sdmmc: dwmmc at 10214000 {
+ compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x10214000 0x4000>;
+ max-frequency = <150000000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ emmc: dwmmc at 1021c000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x1021c000 0x4000>;
+ max-frequency = <150000000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ bus-width = <8>;
+ default-sample-phase = <158>;
+ num-slots = <1>;
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ i2c0: i2c0 at 20072000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <20072000 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ };
+
+ i2c1: i2c1 at 20056000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <0x20056000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ };
+
+ i2c2: i2c2 at 2005a000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <0x2005a000 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ };
+
+ i2c3: i2c3 at 2005e000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <0x2005e000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_xfer>;
+ };
+
+ spi0: spi at 20074000 {
+ compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
+ reg = <0x20074000 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
+ rockchip,spi-src-clk = <0>;
+ num-cs = <2>;
+ clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>;
+ clock-names = "spi","pclk_spi0";
+ dmas = <&pdma 8>, <&pdma 9>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ };
+
+ grf: syscon at 20008000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3128-grf", "syscon";
+ reg = <0x20008000 0x1000>;
+ };
+
+ pinctrl: pinctrl at 20008000 {
+ compatible = "rockchip,rk3128-pinctrl";
+ reg = <0x20008000 0xA8>,
+ <0x200080A8 0x4C>,
+ <0x20008118 0x20>,
+ <0x20008100 0x04>;
+ reg-names = "base", "mux", "pull", "drv";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0 at 2007c000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2007c000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1 at 20080000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20080000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2 at 20084000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20084000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio2 at 20088000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20088000 0x100>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ emmc {
+ /*
+ * We run eMMC at max speed; bump up drive strength.
+ * We also have external pulls, so disable the internal ones.
+ */
+
+ emmc_clk: emmc-clk {
+ rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_pwren: emmc-pwren {
+ rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
+ <1 25 RK_FUNC_2 &pcfg_pull_none>,
+ <1 26 RK_FUNC_2 &pcfg_pull_none>,
+ <1 27 RK_FUNC_2 &pcfg_pull_none>,
+ <1 28 RK_FUNC_2 &pcfg_pull_none>,
+ <1 29 RK_FUNC_2 &pcfg_pull_none>,
+ <1 30 RK_FUNC_2 &pcfg_pull_none>,
+ <1 31 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ nandc{
+ nandc_ale:nandc-ale {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_cle:nandc-cle {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_wrn:nandc-wrn {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_rdn:nandc-rdn {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_rdy:nandc-rdy {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_cs0:nandc-cs0 {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_data: nandc-data {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
+ <0 17 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
+ <2 23 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
+ <1 19 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;
+ };
+
+ sdmmc_wp: sdmmc-wp {
+ rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;
+ };
+
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,
+ <1 RK_PC3 1 &pcfg_pull_up>,
+ <1 RK_PC4 1 &pcfg_pull_up>,
+ <1 RK_PC5 1 &pcfg_pull_up>;
+ };
+ };
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins = <0 1 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <0 27 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
+ <0 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
+ <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins = <2 20 3 &pcfg_pull_none>,
+ <2 21 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
+ <0 7 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ spi0_txd_mux0:spi0-txd-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ spi0_rxd_mux0:spi0-rxd-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ spi0_clk_mux0:spi0-clk-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ spi0_cs0_mux0:spi0-cs0-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ spi0_cs1_mux0:spi0-cs1-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ };
+};
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
new file mode 100644
index 0000000..476268a
--- /dev/null
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+
+/* core clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_GPLL 3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU 64
+#define SCLK_SPI 65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO 69
+#define SCLK_EMMC 71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S 82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER0 85
+#define SCLK_TIMER1 86
+#define SCLK_TIMER2 87
+#define SCLK_TIMER3 88
+#define SCLK_SARADC 91
+#define SCLK_OTGPHY0 93
+#define SCLK_LCDC 100
+#define SCLK_HDMI 109
+#define SCLK_HEVC 111
+#define SCLK_I2S_OUT 113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV 115
+#define SCLK_EMMC_DRV 117
+#define SCLK_SDMMC_SAMPLE 118
+#define SCLK_SDIO_SAMPLE 119
+#define SCLK_EMMC_SAMPLE 121
+#define SCLK_PVTM_CORE 123
+#define SCLK_PVTM_GPU 124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC 151
+#define SCLK_MACREF 152
+#define SCLK_SFC 160
+
+#define DCLK_LCDC 190
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_VIO0 197
+#define ACLK_VIO1 203
+#define ACLK_VCODEC 208
+#define ACLK_CPU 209
+#define ACLK_PERI 210
+
+/* pclk gates */
+#define PCLK_SARADC 318
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GPIO3 323
+#define PCLK_GRF 329
+#define PCLK_I2C0 332
+#define PCLK_I2C1 333
+#define PCLK_I2C2 334
+#define PCLK_I2C3 335
+#define PCLK_SPI 338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM 350
+#define PCLK_TIMER 353
+#define PCLK_HDMI 360
+#define PCLK_CPU 362
+#define PCLK_PERI 363
+#define PCLK_DDRUPCTL 364
+#define PCLK_WDT 368
+
+/* hclk gates */
+#define HCLK_OTG0 449
+#define HCLK_OTG1 450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO 457
+#define HCLK_EMMC 459
+#define HCLK_I2S 462
+#define HCLK_LCDC 465
+#define HCLK_ROM 467
+#define HCLK_VIO_BUS 472
+#define HCLK_VCODEC 476
+#define HCLK_CPU 477
+#define HCLK_PERI 478
+
+#define CLK_NR_CLKS (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C 12
+#define SRST_TOPDBG 13
+#define SRST_STRC_SYS_A 14
+#define SRST_PD_CORE_NIU 15
+
+#define SRST_TIMER2 16
+#define SRST_CPUSYS_H 17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER3 20
+#define SRST_INTMEM 21
+#define SRST_ROM 22
+#define SRST_PERI_NIU 23
+#define SRST_I2S 24
+#define SRST_DDR_PLL 25
+#define SRST_GPU_DLL 26
+#define SRST_TIMER0 27
+#define SRST_TIMER1 28
+#define SRST_CORE_DLL 29
+#define SRST_EFUSE_P 30
+#define SRST_ACODEC_P 31
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_UART0 39
+#define SRST_UART1 40
+#define SRST_UART2 41
+#define SRST_I2C0 43
+#define SRST_I2C1 44
+#define SRST_I2C2 45
+#define SRST_SFC 47
+
+#define SRST_PWM0 48
+#define SRST_DAP 51
+#define SRST_DAP_SYS 52
+#define SRST_GRF 55
+#define SRST_PERIPHSYS_A 57
+#define SRST_PERIPHSYS_H 58
+#define SRST_PERIPHSYS_P 59
+#define SRST_CPU_PERI 61
+#define SRST_EMEM_PERI 62
+#define SRST_USB_PERI 63
+
+#define SRST_DMA2 64
+#define SRST_MAC 66
+#define SRST_NANDC 68
+#define SRST_USBOTG0 69
+#define SRST_OTGC0 71
+#define SRST_USBOTG1 72
+#define SRST_OTGC1 74
+#define SRST_DDRMSCH 79
+
+#define SRST_MMC0 81
+#define SRST_SDIO 82
+#define SRST_EMMC 83
+#define SRST_SPI0 84
+#define SRST_WDT 86
+#define SRST_SARADC 87
+#define SRST_DDRPHY 88
+#define SRST_DDRPHY_P 89
+#define SRST_DDRCTRL 90
+#define SRST_DDRCTRL_P 91
+
+#define SRST_HDMI_P 96
+#define SRST_VIO_BUS_H 99
+#define SRST_UTMI0 103
+#define SRST_UTMI1 104
+#define SRST_USBPOR 105
+
+#define SRST_VCODEC_A 112
+#define SRST_VCODEC_H 113
+#define SRST_VIO1_A 114
+#define SRST_HEVC 115
+#define SRST_VCODEC_NIU_A 116
+#define SRST_LCDC1_A 117
+#define SRST_LCDC1_H 118
+#define SRST_LCDC1_D 119
+#define SRST_GPU 120
+#define SRST_GPU_NIU_A 122
+
+#define SRST_DBG_P 131
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 2/7] rockchip: rk3128: add soc basic support
2017-11-27 9:51 [U-Boot] [PATCH v2 0/7] rockchip: add new SoC support for RK3128 Kever Yang
2017-11-27 9:51 ` [U-Boot] [PATCH v2 1/7] rockchip: rk3128: add device tree file Kever Yang
@ 2017-11-27 9:51 ` Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 3/7] rockchip: rk3128: add clock driver Kever Yang
` (4 subsequent siblings)
6 siblings, 2 replies; 21+ messages in thread
From: Kever Yang @ 2017-11-27 9:51 UTC (permalink / raw)
To: u-boot
RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU
and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host
and device, HDMI/LVDS/MIPI display.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2:
- update setup_boot_mode() with master
- enable board_late_init()
arch/arm/mach-rockchip/Kconfig | 10 ++
arch/arm/mach-rockchip/Makefile | 2 +
arch/arm/mach-rockchip/rk3128-board.c | 127 ++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3128/Kconfig | 0
arch/arm/mach-rockchip/rk3128/Makefile | 8 ++
arch/arm/mach-rockchip/rk3128/rk3128.c | 12 +++
arch/arm/mach-rockchip/rk3128/syscon_rk3128.c | 21 +++++
include/configs/rk3128_common.h | 70 ++++++++++++++
8 files changed, 250 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3128-board.c
create mode 100644 arch/arm/mach-rockchip/rk3128/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3128/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3128/rk3128.c
create mode 100644 arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
create mode 100644 include/configs/rk3128_common.h
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a26736a..1e74db3 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,6 +11,15 @@ config ROCKCHIP_RK3036
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+config ROCKCHIP_RK3128
+ bool "Support Rockchip RK3128"
+ select CPU_V7
+ help
+ The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
+ including NEON and GPU, Mali-400 graphics, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7
@@ -211,6 +220,7 @@ config SPL_MMC_SUPPORT
default y if !SPL_ROCKCHIP_BACK_TO_BROM
source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3128/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk322x/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 7e1f864..e1b0519 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -30,6 +30,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-y += boot_mode.o
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
@@ -43,6 +44,7 @@ obj-y += rk_timer.o
endif
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
endif
diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
new file mode 100644
index 0000000..2e8393d
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128-board.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/grf_rk3128.h>
+#include <asm/arch/boot_mode.h>
+#include <asm/arch/timer.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int rk_board_late_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_boot_mode();
+
+ return rk_board_late_init();
+}
+
+int board_init(void)
+{
+ int ret = 0;
+
+ rockchip_timer_init();
+
+ ret = regulators_enable_boot_on(false);
+ if (ret) {
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x8400000;
+ /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ + gd->bd->bi_dram[0].size + 0xe00000;
+ gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ + gd->ram_size - gd->bd->bi_dram[1].start;
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3128_otg_data = {
+ .rx_fifo_sz = 512,
+ .np_tx_fifo_sz = 16,
+ .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node;
+ const char *mode;
+ bool matched = false;
+ const void *blob = gd->fdt_blob;
+
+ /* find the usb_otg node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3128-usb");
+
+ while (node > 0) {
+ mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "rockchip,rk3128-usb");
+ }
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+ return dwc2_udc_probe(&rk3128_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
+int fb_set_reboot_flag(void)
+{
+ struct rk3128_grf *grf;
+
+ printf("Setting reboot to fastboot flag ...\n");
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ /* Set boot mode to fastboot */
+ writel(BOOT_FASTBOOT, &grf->os_reg[0]);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/mach-rockchip/rk3128/Makefile b/arch/arm/mach-rockchip/rk3128/Makefile
new file mode 100644
index 0000000..0f63d92
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rk3128.o
+obj-y += syscon_rk3128.o
diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c
new file mode 100644
index 0000000..9d6e3b1
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128/rk3128.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+int arch_cpu_init(void)
+{
+ /* We do some SoC one time setting here. */
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
new file mode 100644
index 0000000..0b63639
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3128_syscon_ids[] = {
+ { .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3128) = {
+ .name = "rk3128_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3128_syscon_ids,
+};
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
new file mode 100644
index 0000000..e915a56
--- /dev/null
+++ b/include/configs/rk3128_common.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_RK3128_COMMON_H
+#define __CONFIG_RK3128_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
+#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
+#define CONFIG_SYS_LOAD_ADDR 0x60800800
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_EXT4
+
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CONFIG_NR_DRAM_BANKS 2
+#define SDRAM_MAX_SIZE 0x80000000
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+#ifndef CONFIG_SPL_BUILD
+
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x60500000\0" \
+ "pxefile_addr_r=0x60600000\0" \
+ "fdt_addr_r=0x61f00000\0" \
+ "kernel_addr_r=0x62000000\0" \
+ "ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "partitions=" PARTS_DEFAULT \
+ BOOTENV
+
+#endif
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 3/7] rockchip: rk3128: add clock driver
2017-11-27 9:51 [U-Boot] [PATCH v2 0/7] rockchip: add new SoC support for RK3128 Kever Yang
2017-11-27 9:51 ` [U-Boot] [PATCH v2 1/7] rockchip: rk3128: add device tree file Kever Yang
2017-11-27 9:51 ` [U-Boot] [PATCH v2 2/7] rockchip: rk3128: add soc basic support Kever Yang
@ 2017-11-27 9:51 ` Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot,v2,3/7] " Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 4/7] rockchip: rk3128: add pinctrl driver Kever Yang
` (3 subsequent siblings)
6 siblings, 1 reply; 21+ messages in thread
From: Kever Yang @ 2017-11-27 9:51 UTC (permalink / raw)
To: u-boot
Add rk3128 clock driver and cru structure definition.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2:
- add clock for saradc, vop, nandc, i2c
- update driver bind for sysreset driver and reset driver
- add "rockchip,rk3126-cru" for compatible
arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 212 +++++++++
arch/arm/mach-rockchip/rk3128/Makefile | 1 +
arch/arm/mach-rockchip/rk3128/clk_rk3128.c | 32 ++
drivers/clk/rockchip/Makefile | 3 +-
drivers/clk/rockchip/clk_rk3128.c | 609 ++++++++++++++++++++++++
5 files changed, 856 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3128.h
create mode 100644 arch/arm/mach-rockchip/rk3128/clk_rk3128.c
create mode 100644 drivers/clk/rockchip/clk_rk3128.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
new file mode 100644
index 0000000..cc317dc
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3128_H
+#define _ASM_ARCH_CRU_RK3128_H
+
+#include <common.h>
+
+#define MHz 1000000
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ (600 * MHz)
+#define GPLL_HZ (594 * MHz)
+
+#define CORE_PERI_HZ 150000000
+#define CORE_ACLK_HZ 300000000
+
+#define BUS_ACLK_HZ 148500000
+#define BUS_HCLK_HZ 148500000
+#define BUS_PCLK_HZ 74250000
+
+#define PERI_ACLK_HZ 148500000
+#define PERI_HCLK_HZ 148500000
+#define PERI_PCLK_HZ 74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3128_clk_priv {
+ struct rk3128_cru *cru;
+};
+
+struct rk3128_cru {
+ struct rk3128_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ } pll[4];
+ unsigned int cru_mode_con;
+ unsigned int cru_clksel_con[35];
+ unsigned int cru_clkgate_con[11];
+ unsigned int reserved;
+ unsigned int cru_glb_srst_fst_value;
+ unsigned int cru_glb_srst_snd_value;
+ unsigned int reserved1[2];
+ unsigned int cru_softrst_con[9];
+ unsigned int cru_misc_con;
+ unsigned int reserved2[2];
+ unsigned int cru_glb_cnt_th;
+ unsigned int reserved3[3];
+ unsigned int cru_glb_rst_st;
+ unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
+ unsigned int cru_sdmmc_con[2];
+ unsigned int cru_sdio_con[2];
+ unsigned int reserved5[2];
+ unsigned int cru_emmc_con[2];
+ unsigned int reserved6[4];
+ unsigned int cru_pll_prg_en;
+};
+check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
+
+struct pll_div {
+ u32 refdiv;
+ u32 fbdiv;
+ u32 postdiv1;
+ u32 postdiv2;
+ u32 frac;
+};
+
+enum {
+ /* PLLCON0*/
+ PLL_POSTDIV1_SHIFT = 12,
+ PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
+ PLL_FBDIV_SHIFT = 0,
+ PLL_FBDIV_MASK = 0xfff,
+
+ /* PLLCON1 */
+ PLL_RST_SHIFT = 14,
+ PLL_PD_SHIFT = 13,
+ PLL_PD_MASK = 1 << PLL_PD_SHIFT,
+ PLL_DSMPD_SHIFT = 12,
+ PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
+ PLL_LOCK_STATUS_SHIFT = 10,
+ PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
+ PLL_POSTDIV2_SHIFT = 6,
+ PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
+ PLL_REFDIV_SHIFT = 0,
+ PLL_REFDIV_MASK = 0x3f,
+
+ /* CRU_MODE */
+ GPLL_MODE_SHIFT = 12,
+ GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
+ GPLL_MODE_SLOW = 0,
+ GPLL_MODE_NORM,
+ GPLL_MODE_DEEP,
+ CPLL_MODE_SHIFT = 8,
+ CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
+ CPLL_MODE_SLOW = 0,
+ CPLL_MODE_NORM,
+ DPLL_MODE_SHIFT = 4,
+ DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
+ DPLL_MODE_SLOW = 0,
+ DPLL_MODE_NORM,
+ APLL_MODE_SHIFT = 0,
+ APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
+ APLL_MODE_SLOW = 0,
+ APLL_MODE_NORM,
+
+ /* CRU_CLK_SEL0_CON */
+ BUS_ACLK_PLL_SEL_SHIFT = 14,
+ BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
+ BUS_ACLK_PLL_SEL_CPLL = 0,
+ BUS_ACLK_PLL_SEL_GPLL,
+ BUS_ACLK_PLL_SEL_GPLL_DIV2,
+ BUS_ACLK_PLL_SEL_GPLL_DIV3,
+ BUS_ACLK_DIV_SHIFT = 8,
+ BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
+ CORE_CLK_PLL_SEL_SHIFT = 7,
+ CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
+ CORE_CLK_PLL_SEL_APLL = 0,
+ CORE_CLK_PLL_SEL_GPLL_DIV2,
+ CORE_DIV_CON_SHIFT = 0,
+ CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
+
+ /* CRU_CLK_SEL1_CON */
+ BUS_PCLK_DIV_SHIFT = 12,
+ BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
+ BUS_HCLK_DIV_SHIFT = 8,
+ BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
+ CORE_ACLK_DIV_SHIFT = 4,
+ CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
+ CORE_PERI_DIV_SHIFT = 0,
+ CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
+
+ /* CRU_CLK_SEL2_CON */
+ NANDC_PLL_SEL_SHIFT = 14,
+ NANDC_PLL_SEL_MASK = 7 << NANDC_PLL_SEL_SHIFT,
+ NANDC_PLL_SEL_CPLL = 0,
+ NANDC_PLL_SEL_GPLL,
+ NANDC_CLK_DIV_SHIFT = 8,
+ NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT,
+ PVTM_CLK_DIV_SHIFT = 0,
+ PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT,
+
+ /* CRU_CLKSEL10_CON */
+ PERI_PLL_SEL_SHIFT = 14,
+ PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT,
+ PERI_PLL_APLL = 0,
+ PERI_PLL_DPLL,
+ PERI_PLL_GPLL,
+ PERI_PCLK_DIV_SHIFT = 12,
+ PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
+ PERI_HCLK_DIV_SHIFT = 8,
+ PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
+ PERI_ACLK_DIV_SHIFT = 0,
+ PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
+
+ /* CRU_CLKSEL11_CON */
+ MMC0_PLL_SHIFT = 6,
+ MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
+ MMC0_SEL_APLL = 0,
+ MMC0_SEL_GPLL,
+ MMC0_SEL_GPLL_DIV2,
+ MMC0_SEL_24M,
+ MMC0_DIV_SHIFT = 0,
+ MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
+
+ /* CRU_CLKSEL12_CON */
+ EMMC_PLL_SHIFT = 14,
+ EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
+ EMMC_SEL_APLL = 0,
+ EMMC_SEL_GPLL,
+ EMMC_SEL_GPLL_DIV2,
+ EMMC_SEL_24M,
+ EMMC_DIV_SHIFT = 8,
+ EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
+
+ /* CLKSEL_CON24 */
+ SARADC_DIV_CON_SHIFT = 8,
+ SARADC_DIV_CON_MASK = GENMASK(15, 8),
+ SARADC_DIV_CON_WIDTH = 8,
+
+ /* CRU_CLKSEL27_CON*/
+ DCLK_VOP_SEL_SHIFT = 0,
+ DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
+ DCLK_VOP_PLL_SEL_CPLL = 0,
+ DCLK_VOP_DIV_CON_SHIFT = 8,
+ DCLK_VOP_DIV_CON_MASK = 0xfff << DCLK_VOP_DIV_CON_SHIFT,
+
+ /* CRU_CLKSEL31_CON */
+ VIO0_PLL_SHIFT = 5,
+ VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT,
+ VI00_SEL_CPLL = 0,
+ VIO0_SEL_GPLL,
+ VIO0_DIV_SHIFT = 0,
+ VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT,
+ VIO1_PLL_SHIFT = 13,
+ VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT,
+ VI01_SEL_CPLL = 0,
+ VIO1_SEL_GPLL,
+ VIO1_DIV_SHIFT = 8,
+ VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT,
+
+ /* CRU_SOFTRST5_CON */
+ DDRCTRL_PSRST_SHIFT = 11,
+ DDRCTRL_SRST_SHIFT = 10,
+ DDRPHY_PSRST_SHIFT = 9,
+ DDRPHY_SRST_SHIFT = 8,
+};
+#endif
diff --git a/arch/arm/mach-rockchip/rk3128/Makefile b/arch/arm/mach-rockchip/rk3128/Makefile
index 0f63d92..50e1117 100644
--- a/arch/arm/mach-rockchip/rk3128/Makefile
+++ b/arch/arm/mach-rockchip/rk3128/Makefile
@@ -6,3 +6,4 @@
obj-y += rk3128.o
obj-y += syscon_rk3128.o
+obj-y += clk_rk3128.o
diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c
new file mode 100644
index 0000000..7ca5fd3
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3128.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3128_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3128_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index c50aff2..eae0ef6 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -1,10 +1,11 @@
#
-# Copyright (c) 2016 Google, Inc
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
new file mode 100644
index 0000000..df84f83
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3128.c
@@ -0,0 +1,609 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3128.h>
+#include <asm/arch/hardware.h>
+#include <bitfield.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3128-cru.h>
+#include <linux/log2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ VCO_MAX_HZ = 2400U * 1000000,
+ VCO_MIN_HZ = 600 * 1000000,
+ OUTPUT_MAX_HZ = 2400U * 1000000,
+ OUTPUT_MIN_HZ = 24 * 1000000,
+};
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
+ .refdiv = _refdiv,\
+ .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
+ .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
+
+/* use integer mode*/
+static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
+
+static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id,
+ const struct pll_div *div)
+{
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3128_pll *pll = &cru->pll[pll_id];
+
+ /* All PLLs have same VCO and output frequency range restrictions. */
+ uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
+ uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
+
+ debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n",
+ pll, div->fbdiv, div->refdiv, div->postdiv1,
+ div->postdiv2, vco_hz, output_hz);
+ assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
+ output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
+
+ /* use integer mode */
+ rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+ /* Power down */
+ rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
+
+ rk_clrsetreg(&pll->con0,
+ PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
+ (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
+ rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+ (div->postdiv2 << PLL_POSTDIV2_SHIFT |
+ div->refdiv << PLL_REFDIV_SHIFT));
+
+ /* Power Up */
+ rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
+
+ /* waiting for pll lock */
+ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
+ udelay(1);
+
+ return 0;
+}
+
+static int pll_para_config(u32 freq_hz, struct pll_div *div)
+{
+ u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0;
+ u32 postdiv1, postdiv2 = 1;
+ u32 fref_khz;
+ u32 diff_khz, best_diff_khz;
+ const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
+ const u32 max_postdiv1 = 7, max_postdiv2 = 7;
+ u32 vco_khz;
+ u32 freq_khz = freq_hz / 1000;
+
+ if (!freq_hz) {
+ printf("%s: the frequency can't be 0 Hz\n", __func__);
+ return -1;
+ }
+
+ postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz);
+ if (postdiv1 > max_postdiv1) {
+ postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
+ postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
+ }
+
+ vco_khz = freq_khz * postdiv1 * postdiv2;
+
+ if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) ||
+ postdiv2 > max_postdiv2) {
+ printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n",
+ __func__, freq_hz);
+ return -1;
+ }
+
+ div->postdiv1 = postdiv1;
+ div->postdiv2 = postdiv2;
+
+ best_diff_khz = vco_khz;
+ for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
+ fref_khz = ref_khz / refdiv;
+
+ fbdiv = vco_khz / fref_khz;
+ if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
+ continue;
+ diff_khz = vco_khz - fbdiv * fref_khz;
+ if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
+ fbdiv++;
+ diff_khz = fref_khz - diff_khz;
+ }
+
+ if (diff_khz >= best_diff_khz)
+ continue;
+
+ best_diff_khz = diff_khz;
+ div->refdiv = refdiv;
+ div->fbdiv = fbdiv;
+ }
+
+ if (best_diff_khz > 4 * (1000)) {
+ printf("%s: Failed to match output frequency %u bestis %u Hz\n",
+ __func__, freq_hz,
+ best_diff_khz * 1000);
+ return -1;
+ }
+ return 0;
+}
+
+static void rkclk_init(struct rk3128_cru *cru)
+{
+ u32 aclk_div;
+ u32 hclk_div;
+ u32 pclk_div;
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK | APLL_MODE_MASK,
+ GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
+ APLL_MODE_SLOW << APLL_MODE_SHIFT);
+
+ /* init pll */
+ rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
+ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
+
+ /*
+ * select apll as cpu/core clock pll source and
+ * set up dependent divisors for PERI and ACLK clocks.
+ * core hz : apll = 1:1
+ */
+ aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
+ assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
+
+ pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
+ assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
+ CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+ 0 << CORE_DIV_CON_SHIFT);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
+ aclk_div << CORE_ACLK_DIV_SHIFT |
+ pclk_div << CORE_PERI_DIV_SHIFT);
+
+ /*
+ * select gpll as pd_bus bus clock source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
+ assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
+
+ pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
+ assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
+
+ hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
+ assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
+ BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
+ aclk_div << BUS_ACLK_DIV_SHIFT);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
+ pclk_div << BUS_PCLK_DIV_SHIFT |
+ hclk_div << BUS_HCLK_DIV_SHIFT);
+
+ /*
+ * select gpll as pd_peri bus clock source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
+ assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+ hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+ assert((1 << hclk_div) * PERI_HCLK_HZ ==
+ PERI_ACLK_HZ && (hclk_div < 0x4));
+
+ pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+ assert((1 << pclk_div) * PERI_PCLK_HZ ==
+ PERI_ACLK_HZ && pclk_div < 0x8);
+
+ rk_clrsetreg(&cru->cru_clksel_con[10],
+ PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
+ PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
+ PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
+ pclk_div << PERI_PCLK_DIV_SHIFT |
+ hclk_div << PERI_HCLK_DIV_SHIFT |
+ aclk_div << PERI_ACLK_DIV_SHIFT);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK | APLL_MODE_MASK | CPLL_MODE_MASK,
+ GPLL_MODE_NORM << GPLL_MODE_SHIFT |
+ APLL_MODE_NORM << APLL_MODE_SHIFT |
+ CPLL_MODE_NORM << CPLL_MODE_SHIFT);
+
+ /*fix NAND controller working clock max to 150Mhz */
+ rk_clrsetreg(&cru->cru_clksel_con[2],
+ NANDC_PLL_SEL_MASK | NANDC_CLK_DIV_MASK,
+ NANDC_PLL_SEL_GPLL << NANDC_PLL_SEL_SHIFT |
+ 3 << NANDC_CLK_DIV_SHIFT);
+}
+
+/* Get pll rate by id */
+static u32 rkclk_pll_get_rate(struct rk3128_cru *cru,
+ enum rk_clk_id clk_id)
+{
+ u32 refdiv, fbdiv, postdiv1, postdiv2;
+ u32 con;
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3128_pll *pll = &cru->pll[pll_id];
+ static u8 clk_shift[CLK_COUNT] = {
+ 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
+ GPLL_MODE_SHIFT, 0xff
+ };
+ static u32 clk_mask[CLK_COUNT] = {
+ 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
+ GPLL_MODE_MASK, 0xff
+ };
+ uint shift;
+ uint mask;
+
+ con = readl(&cru->cru_mode_con);
+ shift = clk_shift[clk_id];
+ mask = clk_mask[clk_id];
+
+ switch ((con & mask) >> shift) {
+ case GPLL_MODE_SLOW:
+ return OSC_HZ;
+ case GPLL_MODE_NORM:
+ /* normal mode */
+ con = readl(&pll->con0);
+ postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
+ fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
+ con = readl(&pll->con1);
+ postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
+ refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
+ return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
+ case GPLL_MODE_DEEP:
+ default:
+ return 32768;
+ }
+}
+
+static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
+ int periph)
+{
+ uint src_rate;
+ uint div, mux;
+ u32 con;
+
+ switch (periph) {
+ case HCLK_EMMC:
+ case SCLK_EMMC:
+ case SCLK_EMMC_SAMPLE:
+ con = readl(&cru->cru_clksel_con[12]);
+ mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
+ div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
+ break;
+ case HCLK_SDMMC:
+ case SCLK_SDMMC:
+ con = readl(&cru->cru_clksel_con[11]);
+ mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
+ div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
+ return DIV_TO_RATE(src_rate, div);
+}
+
+static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
+ int periph, uint freq)
+{
+ int src_clk_div;
+ int mux;
+
+ debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
+
+ /* mmc clock defaulg div 2 internal, need provide double in cru */
+ src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
+
+ if (src_clk_div > 128) {
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+ mux = EMMC_SEL_24M;
+ } else {
+ mux = EMMC_SEL_GPLL;
+ }
+
+ switch (periph) {
+ case HCLK_EMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[12],
+ EMMC_PLL_MASK | EMMC_DIV_MASK,
+ mux << EMMC_PLL_SHIFT |
+ (src_clk_div - 1) << EMMC_DIV_SHIFT);
+ break;
+ case HCLK_SDMMC:
+ case SCLK_SDMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[11],
+ MMC0_PLL_MASK | MMC0_DIV_MASK,
+ mux << MMC0_PLL_SHIFT |
+ (src_clk_div - 1) << MMC0_DIV_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
+}
+
+static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id)
+{
+ u32 div, con;
+
+ switch (clk_id) {
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_PWM:
+ con = readl(&cru->cru_clksel_con[10]);
+ div = con >> 12 & 0x3;
+ break;
+ default:
+ printf("do not support this peripheral bus\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(PERI_ACLK_HZ, div);
+}
+
+static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = PERI_ACLK_HZ / hz;
+ assert(src_clk_div - 1 < 4);
+
+ switch (clk_id) {
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_PWM:
+ rk_setreg(&cru->cru_clksel_con[10],
+ ((src_clk_div - 1) << 12));
+ break;
+ default:
+ printf("do not support this peripheral bus\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div);
+}
+
+static ulong rk3128_saradc_get_clk(struct rk3128_cru *cru)
+{
+ u32 div, val;
+
+ val = readl(&cru->cru_clksel_con[24]);
+ div = bitfield_extract(val, SARADC_DIV_CON_SHIFT,
+ SARADC_DIV_CON_WIDTH);
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+ assert(src_clk_div < 128);
+
+ rk_clrsetreg(&cru->cru_clksel_con[24],
+ SARADC_DIV_CON_MASK,
+ src_clk_div << SARADC_DIV_CON_SHIFT);
+
+ return rk3128_saradc_get_clk(cru);
+}
+
+static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz)
+{
+ int src_clk_div;
+ struct pll_div cpll_config = {0};
+
+ src_clk_div = GPLL_HZ / hz;
+ assert(src_clk_div - 1 < 31);
+
+ switch (clk_id) {
+ case ACLK_VIO0:
+ rk_clrsetreg(&cru->cru_clksel_con[31],
+ VIO0_PLL_MASK | VIO0_DIV_MASK,
+ VIO0_SEL_GPLL << VIO0_PLL_SHIFT |
+ (src_clk_div - 1) << VIO0_DIV_SHIFT);
+ break;
+ case ACLK_VIO1:
+ rk_clrsetreg(&cru->cru_clksel_con[31],
+ VIO1_PLL_MASK | VIO1_DIV_MASK,
+ VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
+ (src_clk_div - 1) << VIO1_DIV_SHIFT);
+ break;
+ case DCLK_LCDC:
+ if (pll_para_config(hz, &cpll_config))
+ return -1;
+ rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
+
+ rk_clrsetreg(&cru->cru_clksel_con[27],
+ DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_CON_MASK,
+ DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_SEL_SHIFT |
+ (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
+ break;
+ default:
+ printf("do not support this vop freq\n");
+ return -EINVAL;
+ }
+
+ return hz;
+}
+
+static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
+{
+ u32 div, con, parent;
+
+ switch (clk_id) {
+ case ACLK_VIO0:
+ con = readl(&cru->cru_clksel_con[31]);
+ div = con & 0x1f;
+ parent = GPLL_HZ;
+ break;
+ case ACLK_VIO1:
+ con = readl(&cru->cru_clksel_con[31]);
+ div = (con >> 8) & 0x1f;
+ parent = GPLL_HZ;
+ break;
+ case DCLK_LCDC:
+ con = readl(&cru->cru_clksel_con[27]);
+ div = (con >> 8) & 0xfff;
+ parent = rkclk_pll_get_rate(cru, CLK_CODEC);
+ break;
+ default:
+ return -ENOENT;
+ }
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3128_clk_get_rate(struct clk *clk)
+{
+ struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case 0 ... 63:
+ return rkclk_pll_get_rate(priv->cru, clk->id);
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_PWM:
+ return rk3128_peri_get_pclk(priv->cru, clk->id);
+ case SCLK_SARADC:
+ return rk3128_saradc_get_clk(priv->cru);
+ case DCLK_LCDC:
+ case ACLK_VIO0:
+ case ACLK_VIO1:
+ return rk3128_vop_get_rate(priv->cru, clk->id);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong new_rate, gclk_rate;
+
+ gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+ switch (clk->id) {
+ case 0 ... 63:
+ return 0;
+ case DCLK_LCDC:
+ case ACLK_VIO0:
+ case ACLK_VIO1:
+ new_rate = rk3128_vop_set_clk(priv->cru,
+ clk->id, rate);
+ break;
+ case HCLK_EMMC:
+ new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
+ clk->id, rate);
+ break;
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_PWM:
+ new_rate = rk3128_peri_set_pclk(priv->cru, clk->id, rate);
+ break;
+ case SCLK_SARADC:
+ new_rate = rk3128_saradc_set_clk(priv->cru, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+static struct clk_ops rk3128_clk_ops = {
+ .get_rate = rk3128_clk_get_rate,
+ .set_rate = rk3128_clk_set_rate,
+};
+
+static int rk3128_clk_probe(struct udevice *dev)
+{
+ struct rk3128_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = (struct rk3128_cru *)dev_read_addr(dev);
+ rkclk_init(priv->cru);
+
+ return 0;
+}
+
+static int rk3128_clk_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *sys_child, *sf_child;
+ struct sysreset_reg *priv;
+ struct softreset_reg *sf_priv;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3128_cru,
+ cru_glb_srst_fst_value);
+ priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
+ cru_glb_srst_snd_value);
+ sys_child->priv = priv;
+ }
+
+ ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
+ dev_ofnode(dev), &sf_child);
+ if (ret) {
+ debug("Warning: No rockchip reset driver: ret=%d\n", ret);
+ } else {
+ sf_priv = malloc(sizeof(struct softreset_reg));
+ sf_priv->sf_reset_offset = offsetof(struct rk3128_cru,
+ cru_softrst_con[0]);
+ sf_priv->sf_reset_num = 9;
+ sf_child->priv = sf_priv;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id rk3128_clk_ids[] = {
+ { .compatible = "rockchip,rk3128-cru" },
+ { .compatible = "rockchip,rk3126-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3128_cru) = {
+ .name = "clk_rk3128",
+ .id = UCLASS_CLK,
+ .of_match = rk3128_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
+ .ops = &rk3128_clk_ops,
+ .bind = rk3128_clk_bind,
+ .probe = rk3128_clk_probe,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 4/7] rockchip: rk3128: add pinctrl driver
2017-11-27 9:51 [U-Boot] [PATCH v2 0/7] rockchip: add new SoC support for RK3128 Kever Yang
` (2 preceding siblings ...)
2017-11-27 9:51 ` [U-Boot] [PATCH v2 3/7] rockchip: rk3128: add clock driver Kever Yang
@ 2017-11-27 9:51 ` Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot,v2,4/7] " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 5/7] rockchip: rk3128: add evb-rk3128 support Kever Yang
` (2 subsequent siblings)
6 siblings, 2 replies; 21+ messages in thread
From: Kever Yang @ 2017-11-27 9:51 UTC (permalink / raw)
To: u-boot
Add rk3128 pinctrl driver and grf/iomux structure definition.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2:
- remove debug info
- update GPIO2C4/C5 SHIFT
arch/arm/include/asm/arch-rockchip/grf_rk3128.h | 551 ++++++++++++++++++++++++
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/rockchip/Makefile | 4 +-
drivers/pinctrl/rockchip/pinctrl_rk3128.c | 187 ++++++++
4 files changed, 750 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3128.h
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3128.h b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h
new file mode 100644
index 0000000..aa6b693
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h
@@ -0,0 +1,551 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK3128_H
+#define _ASM_ARCH_GRF_RK3128_H
+
+#include <common.h>
+
+struct rk3128_grf {
+ unsigned int reserved[0x2a];
+ unsigned int gpio0a_iomux;
+ unsigned int gpio0b_iomux;
+ unsigned int gpio0c_iomux;
+ unsigned int gpio0d_iomux;
+ unsigned int gpio1a_iomux;
+ unsigned int gpio1b_iomux;
+ unsigned int gpio1c_iomux;
+ unsigned int gpio1d_iomux;
+ unsigned int gpio2a_iomux;
+ unsigned int gpio2b_iomux;
+ unsigned int gpio2c_iomux;
+ unsigned int gpio2d_iomux;
+ unsigned int gpio3a_iomux;
+ unsigned int gpio3b_iomux;
+ unsigned int gpio3c_iomux;
+ unsigned int gpio3d_iomux;
+ unsigned int gpio2c_iomux2;
+ unsigned int grf_cif_iomux;
+ unsigned int grf_cif_iomux1;
+ unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
+ unsigned int gpio0l_pull;
+ unsigned int gpio0h_pull;
+ unsigned int gpio1l_pull;
+ unsigned int gpio1h_pull;
+ unsigned int gpio2l_pull;
+ unsigned int gpio2h_pull;
+ unsigned int gpio3l_pull;
+ unsigned int gpio3h_pull;
+ unsigned int reserved2;
+ unsigned int soc_con0;
+ unsigned int soc_con1;
+ unsigned int soc_con2;
+ unsigned int soc_status0;
+ unsigned int reserved3[6];
+ unsigned int mac_con0;
+ unsigned int mac_con1;
+ unsigned int reserved4[4];
+ unsigned int uoc0_con0;
+ unsigned int reserved5;
+ unsigned int uoc1_con1;
+ unsigned int uoc1_con2;
+ unsigned int uoc1_con3;
+ unsigned int uoc1_con4;
+ unsigned int uoc1_con5;
+ unsigned int reserved6;
+ unsigned int ddrc_stat;
+ unsigned int reserved9;
+ unsigned int soc_status1;
+ unsigned int cpu_con0;
+ unsigned int cpu_con1;
+ unsigned int cpu_con2;
+ unsigned int cpu_con3;
+ unsigned int reserved10;
+ unsigned int reserved11;
+ unsigned int cpu_status0;
+ unsigned int cpu_status1;
+ unsigned int os_reg[8];
+ unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
+ unsigned int usbphy0_con[8];
+ unsigned int usbphy1_con[8];
+ unsigned int uoc_status0;
+ unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
+ unsigned int chip_tag;
+ unsigned int sdmmc_det_cnt;
+};
+check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
+
+struct rk3128_pmu {
+ unsigned int wakeup_cfg;
+ unsigned int pwrdn_con;
+ unsigned int pwrdn_st;
+ unsigned int idle_req;
+ unsigned int idle_st;
+ unsigned int pwrmode_con;
+ unsigned int pwr_state;
+ unsigned int osc_cnt;
+ unsigned int core_pwrdwn_cnt;
+ unsigned int core_pwrup_cnt;
+ unsigned int sft_con;
+ unsigned int ddr_sref_st;
+ unsigned int int_con;
+ unsigned int int_st;
+ unsigned int sys_reg[4];
+};
+check_member(rk3128_pmu, int_st, 0x34);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+ GPIO0A7_SHIFT = 14,
+ GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
+ GPIO0A7_GPIO = 0,
+ GPIO0A7_I2C3_SDA,
+
+ GPIO0A6_SHIFT = 12,
+ GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
+ GPIO0A6_GPIO = 0,
+ GPIO0A6_I2C3_SCL,
+
+ GPIO0A3_SHIFT = 6,
+ GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
+ GPIO0A3_GPIO = 0,
+ GPIO0A3_I2C1_SDA,
+
+ GPIO0A2_SHIFT = 4,
+ GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
+ GPIO0A2_GPIO = 0,
+ GPIO0A2_I2C1_SCL,
+
+ GPIO0A1_SHIFT = 2,
+ GPIO0A1_MASK = 1 << GPIO0A1_SHIFT,
+ GPIO0A1_GPIO = 0,
+ GPIO0A1_I2C0_SDA,
+
+ GPIO0A0_SHIFT = 0,
+ GPIO0A0_MASK = 1 << GPIO0A0_SHIFT,
+ GPIO0A0_GPIO = 0,
+ GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+ GPIO0B6_SHIFT = 12,
+ GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
+ GPIO0B6_GPIO = 0,
+ GPIO0B6_I2S_SDI,
+ GPIO0B6_SPI_CSN0,
+
+ GPIO0B5_SHIFT = 10,
+ GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
+ GPIO0B5_GPIO = 0,
+ GPIO0B5_I2S_SDO,
+ GPIO0B5_SPI_RXD,
+
+ GPIO0B4_SHIFT = 8,
+ GPIO0B4_MASK = 1 << GPIO0B4_SHIFT,
+ GPIO0B4_GPIO = 0,
+ GPIO0B4_I2S_LRCKTX,
+
+ GPIO0B3_SHIFT = 6,
+ GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
+ GPIO0B3_GPIO = 0,
+ GPIO0B3_I2S_LRCKRX,
+ GPIO0B3_SPI_TXD,
+
+ GPIO0B1_SHIFT = 2,
+ GPIO0B1_MASK = 3,
+ GPIO0B1_GPIO = 0,
+ GPIO0B1_I2S_SCLK,
+ GPIO0B1_SPI_CLK,
+
+ GPIO0B0_SHIFT = 0,
+ GPIO0B0_MASK = 3,
+ GPIO0B0_GPIO = 0,
+ GPIO0B0_I2S1_MCLK,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_PWM2,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_PWM1,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_PWM0,
+
+ GPIO0D1_SHIFT = 2,
+ GPIO0D1_MASK = 1 << GPIO0D1_SHIFT,
+ GPIO0D1_GPIO = 0,
+ GPIO0D1_UART2_CTSN,
+
+ GPIO0D0_SHIFT = 0,
+ GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
+ GPIO0D0_GPIO = 0,
+ GPIO0D0_UART2_RTSN,
+ GPIO0D0_PMIC_SLEEP,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A5_SHIFT = 10,
+ GPIO1A5_MASK = 3 << GPIO1A5_SHIFT,
+ GPIO1A5_GPIO = 0,
+ GPIO1A5_I2S_SDI,
+ GPIO1A5_SDMMC_DATA3,
+
+ GPIO1A4_SHIFT = 8,
+ GPIO1A4_MASK = 3 << GPIO1A4_SHIFT,
+ GPIO1A4_GPIO = 0,
+ GPIO1A4_I2S_SD0,
+ GPIO1A4_SDMMC_DATA2,
+
+ GPIO1A3_SHIFT = 6,
+ GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
+ GPIO1A3_GPIO = 0,
+ GPIO1A3_I2S_LRCKTX,
+
+ GPIO1A2_SHIFT = 4,
+ GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
+ GPIO1A2_GPIO = 0,
+ GPIO1A2_I2S_LRCKRX,
+ GPIO1A2_SDMMC_DATA1,
+
+ GPIO1A1_SHIFT = 2,
+ GPIO1A1_MASK = 3 << GPIO1A1_SHIFT,
+ GPIO1A1_GPIO = 0,
+ GPIO1A1_I2S_SCLK,
+ GPIO1A1_SDMMC_DATA0,
+ GPIO1A1_PMIC_SLEEP,
+
+ GPIO1A0_SHIFT = 0,
+ GPIO1A0_MASK = 3,
+ GPIO1A0_GPIO = 0,
+ GPIO1A0_I2S_MCLK,
+ GPIO1A0_SDMMC_CLKOUT,
+ GPIO1A0_XIN32K,
+
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_MMC0_CMD,
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = 1 << GPIO1B6_SHIFT,
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_MMC_PWREN,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_SPI_RXD,
+ GPIO1B2_UART1_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_SPI_TXD,
+ GPIO1B1_UART1_SOUT,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 3 << GPIO1B0_SHIFT,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_SPI_CLK,
+ GPIO1B0_UART1_CTSN
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C6_SHIFT = 12,
+ GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_NAND_CS2,
+ GPIO1C6_EMMC_CMD,
+
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_MMC0_D3,
+ GPIO1C5_JTAG_TMS,
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_MMC0_D2,
+ GPIO1C4_JTAG_TCK,
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_MMC0_D1,
+ GPIO1C3_UART2_RX,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_MMC0_D0,
+ GPIO1C2_UART2_TX,
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_MMC0_DETN,
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_MMC0_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_NAND_D7,
+ GPIO1D7_EMMC_D7,
+ GPIO1D7_SPI_CSN1,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_NAND_D6,
+ GPIO1D6_EMMC_D6,
+ GPIO1D6_SPI_CSN0,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_NAND_D5,
+ GPIO1D5_EMMC_D5,
+ GPIO1D5_SPI_TXD1,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_NAND_D4,
+ GPIO1D4_EMMC_D4,
+ GPIO1D4_SPI_RXD1,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_NAND_D3,
+ GPIO1D3_EMMC_D3,
+ GPIO1D3_SFC_SIO3,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_NAND_D2,
+ GPIO1D2_EMMC_D2,
+ GPIO1D2_SFC_SIO2,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_NAND_D1,
+ GPIO1D1_EMMC_D1,
+ GPIO1D1_SFC_SIO1,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_NAND_D0,
+ GPIO1D0_EMMC_D0,
+ GPIO1D0_SFC_SIO0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_NAND_DQS,
+ GPIO2A7_EMMC_CLKOUT,
+
+ GPIO2A6_SHIFT = 12,
+ GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_NAND_CS0,
+
+ GPIO2A5_SHIFT = 10,
+ GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_NAND_WP,
+ GPIO2A5_EMMC_PWREN,
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_NAND_RDY,
+ GPIO2A4_EMMC_CMD,
+ GPIO2A3_SFC_CLK,
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_NAND_RDN,
+ GPIO2A4_SFC_CSN1,
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_NAND_WRN,
+ GPIO2A4_SFC_CSN0,
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_NAND_CLE,
+ GPIO2A1_EMMC_CLKOUT,
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_NAND_ALE,
+ GPIO2A0_SPI_CLK,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+ GPIO2B7_SHIFT = 14,
+ GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
+ GPIO2B7_GPIO = 0,
+ GPIO2B7_LCDC0_D13,
+ GPIO2B7_EBC_SDCE5,
+ GPIO2B7_GMAC_RXER,
+
+ GPIO2B6_SHIFT = 12,
+ GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
+ GPIO2B6_GPIO = 0,
+ GPIO2B6_LCDC0_D12,
+ GPIO2B6_EBC_SDCE4,
+ GPIO2B6_GMAC_CLK,
+
+ GPIO2B5_SHIFT = 10,
+ GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
+ GPIO2B5_GPIO = 0,
+ GPIO2B5_LCDC0_D11,
+ GPIO2B5_EBC_SDCE3,
+ GPIO2B5_GMAC_TXEN,
+
+ GPIO2B4_SHIFT = 8,
+ GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
+ GPIO2B4_GPIO = 0,
+ GPIO2B4_LCDC0_D10,
+ GPIO2B4_EBC_SDCE2,
+ GPIO2B4_GMAC_MDIO,
+
+ GPIO2B3_SHIFT = 6,
+ GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
+ GPIO2B3_GPIO = 0,
+ GPIO2B3_LCDC0_DEN,
+ GPIO2B3_EBC_GDCLK,
+ GPIO2B3_GMAC_RXCLK,
+
+ GPIO2B2_SHIFT = 4,
+ GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
+ GPIO2B2_GPIO = 0,
+ GPIO2B2_LCDC0_VSYNC,
+ GPIO2B2_EBC_SDOE,
+ GPIO2B2_GMAC_CRS,
+
+ GPIO2B1_SHIFT = 2,
+ GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
+ GPIO2B1_GPIO = 0,
+ GPIO2B1_LCDC0_HSYNC,
+ GPIO2B1_EBC_SDLE,
+ GPIO2B1_GMAC_TXCLK,
+
+ GPIO2B0_SHIFT = 0,
+ GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
+ GPIO2B0_GPIO = 0,
+ GPIO2B0_LCDC0_DCLK,
+ GPIO2B0_EBC_SDCLK,
+ GPIO2B0_GMAC_RXDV,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C3_SHIFT = 6,
+ GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
+ GPIO2C3_GPIO = 0,
+ GPIO2C3_LCDC0_D17,
+ GPIO2C3_EBC_GDPWR0,
+ GPIO2C3_GMAC_TXD0,
+
+ GPIO2C2_SHIFT = 4,
+ GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
+ GPIO2C2_GPIO = 0,
+ GPIO2C2_LCDC0_D16,
+ GPIO2C2_EBC_GDSP,
+ GPIO2C2_GMAC_TXD1,
+
+ GPIO2C1_SHIFT = 2,
+ GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
+ GPIO2C1_GPIO = 0,
+ GPIO2C1_LCDC0_D15,
+ GPIO2C1_EBC_GDOE,
+ GPIO2C1_GMAC_RXD0,
+
+ GPIO2C0_SHIFT = 0,
+ GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
+ GPIO2C0_GPIO = 0,
+ GPIO2C0_LCDC0_D14,
+ GPIO2C0_EBC_VCOM,
+ GPIO2C0_GMAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D6_SHIFT = 12,
+ GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_LCDC0_D22,
+ GPIO2D6_GMAC_COL = 4,
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_GMAC_MDC = 3,
+};
+
+/* GRF_GPIO2C_IOMUX2 */
+enum {
+ GPIO2C7_SHIFT = 12,
+ GPIO2C7_MASK = 7 << GPIO2C7_SHIFT,
+ GPIO2C7_GPIO = 0,
+ GPIO2C7_GMAC_TXD3 = 4,
+
+ GPIO2C6_SHIFT = 12,
+ GPIO2C6_MASK = 7 << GPIO2C6_SHIFT,
+ GPIO2C6_GPIO = 0,
+ GPIO2C6_GMAC_TXD2 = 4,
+
+ GPIO2C5_SHIFT = 4,
+ GPIO2C5_MASK = 7 << GPIO2C5_SHIFT,
+ GPIO2C5_GPIO = 0,
+ GPIO2C5_I2C2_SCL = 3,
+ GPIO2C5_GMAC_RXD2,
+
+ GPIO2C4_SHIFT = 0,
+ GPIO2C4_MASK = 7 << GPIO2C4_SHIFT,
+ GPIO2C4_GPIO = 0,
+ GPIO2C4_I2C2_SDA = 3,
+ GPIO2C4_GMAC_RXD2,
+};
+#endif
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index afca56d..7e8e4b0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -168,6 +168,16 @@ config PINCTRL_ROCKCHIP_RK3036
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_ROCKCHIP_RK3128
+ bool "Rockchip rk3128 pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rk3128 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
config PINCTRL_ROCKCHIP_RK3188
bool "Rockchip rk3188 pin control driver"
depends on DM
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 5251771..f09c6e1 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -1,11 +1,11 @@
#
-# Copyright (c) 2015 Google, Inc
-# Written by Simon Glass <sjg@chromium.org>
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
+obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3128) += pinctrl_rk3128.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3128.c b/drivers/pinctrl/rockchip/pinctrl_rk3128.c
new file mode 100644
index 0000000..b1c32ac
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3128.c
@@ -0,0 +1,187 @@
+/*
+ * Pinctrl driver for Rockchip 3128 SoCs
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3128.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3128_pinctrl_priv {
+ struct rk3128_grf *grf;
+};
+
+static void pinctrl_rk3128_i2c_config(struct rk3128_grf *grf, int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A1_MASK | GPIO0A0_MASK,
+ GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
+ GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
+
+ break;
+ case PERIPH_ID_I2C1:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A3_MASK | GPIO0A2_MASK,
+ GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
+ GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
+ break;
+ case PERIPH_ID_I2C2:
+ rk_clrsetreg(&grf->gpio2c_iomux2,
+ GPIO2C5_MASK | GPIO2C4_MASK,
+ GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
+ GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
+ break;
+ case PERIPH_ID_I2C3:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A7_MASK | GPIO0A6_MASK,
+ GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
+ GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
+
+ break;
+ }
+}
+
+static void pinctrl_rk3128_sdmmc_config(struct rk3128_grf *grf, int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
+ GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
+ GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
+ GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
+ GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
+ GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
+ GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
+ GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
+ GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A5_MASK | GPIO2A7_MASK,
+ GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
+ GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
+ break;
+ case PERIPH_ID_SDCARD:
+ rk_clrsetreg(&grf->gpio1c_iomux, 0x0fff,
+ GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
+ GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
+ GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
+ GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
+ GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
+ GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
+ break;
+ }
+}
+
+static int rk3128_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ pinctrl_rk3128_i2c_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ pinctrl_rk3128_sdmmc_config(priv->grf, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rk3128_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[3];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[1]) {
+ case 14:
+ return PERIPH_ID_SDCARD;
+ case 16:
+ return PERIPH_ID_EMMC;
+ case 20:
+ return PERIPH_ID_UART0;
+ case 21:
+ return PERIPH_ID_UART1;
+ case 22:
+ return PERIPH_ID_UART2;
+ case 23:
+ return PERIPH_ID_SPI0;
+ case 24:
+ return PERIPH_ID_I2C0;
+ case 25:
+ return PERIPH_ID_I2C1;
+ case 26:
+ return PERIPH_ID_I2C2;
+ case 27:
+ return PERIPH_ID_I2C3;
+ case 30:
+ return PERIPH_ID_PWM0;
+ }
+ return -ENOENT;
+}
+
+static int rk3128_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = rk3128_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+ return rk3128_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk3128_pinctrl_ops = {
+ .set_state_simple = rk3128_pinctrl_set_state_simple,
+ .request = rk3128_pinctrl_request,
+ .get_periph_id = rk3128_pinctrl_get_periph_id,
+};
+
+static int rk3128_pinctrl_probe(struct udevice *dev)
+{
+ struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ debug("%s: grf=%p\n", __func__, priv->grf);
+ return 0;
+}
+
+static const struct udevice_id rk3128_pinctrl_ids[] = {
+ { .compatible = "rockchip,rk3128-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3128) = {
+ .name = "pinctrl_rk3128",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3128_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3128_pinctrl_priv),
+ .ops = &rk3128_pinctrl_ops,
+ .bind = dm_scan_fdt_dev,
+ .probe = rk3128_pinctrl_probe,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 5/7] rockchip: rk3128: add evb-rk3128 support
2017-11-27 9:51 [U-Boot] [PATCH v2 0/7] rockchip: add new SoC support for RK3128 Kever Yang
` (3 preceding siblings ...)
2017-11-27 9:51 ` [U-Boot] [PATCH v2 4/7] rockchip: rk3128: add pinctrl driver Kever Yang
@ 2017-11-27 9:51 ` Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-27 19:30 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 6/7] rockchip: rk3128: add defconfig for evb-rk3128 Kever Yang
2017-11-27 9:51 ` [U-Boot] [PATCH v2 7/7] rockchip: rk3128: add sdram driver Kever Yang
6 siblings, 2 replies; 21+ messages in thread
From: Kever Yang @ 2017-11-27 9:51 UTC (permalink / raw)
To: u-boot
evb-rk3128 is an evb from Rockchip based on rk3128 SoC:
- 2 USB2.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2:
- enable usb nodes
arch/arm/mach-rockchip/rk3128/Kconfig | 24 ++++++++++++++++++++++++
board/rockchip/evb_rk3128/Kconfig | 15 +++++++++++++++
board/rockchip/evb_rk3128/MAINTAINERS | 6 ++++++
board/rockchip/evb_rk3128/Makefile | 7 +++++++
board/rockchip/evb_rk3128/evb-rk3128.c | 9 +++++++++
include/configs/evb_rk3128.h | 15 +++++++++++++++
6 files changed, 76 insertions(+)
create mode 100644 board/rockchip/evb_rk3128/Kconfig
create mode 100644 board/rockchip/evb_rk3128/MAINTAINERS
create mode 100644 board/rockchip/evb_rk3128/Makefile
create mode 100644 board/rockchip/evb_rk3128/evb-rk3128.c
create mode 100644 include/configs/evb_rk3128.h
diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig
index e69de29..40655a2 100644
--- a/arch/arm/mach-rockchip/rk3128/Kconfig
+++ b/arch/arm/mach-rockchip/rk3128/Kconfig
@@ -0,0 +1,24 @@
+if ROCKCHIP_RK3128
+
+choice
+ prompt "RK3128 board select"
+
+config TARGET_EVB_RK3128
+ bool "RK3128 evaluation board"
+ select BOARD_LATE_INIT
+ help
+ RK3128evb is a evaluation board for Rockchip rk3128,
+ with full function and phisical connectors support like
+ usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
+
+endchoice
+
+config SYS_SOC
+ default "rockchip"
+
+config SYS_MALLOC_F_LEN
+ default 0x0800
+
+source "board/rockchip/evb_rk3128/Kconfig"
+
+endif
diff --git a/board/rockchip/evb_rk3128/Kconfig b/board/rockchip/evb_rk3128/Kconfig
new file mode 100644
index 0000000..5b3095a
--- /dev/null
+++ b/board/rockchip/evb_rk3128/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3128
+
+config SYS_BOARD
+ default "evb_rk3128"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "evb_rk3128"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3128/MAINTAINERS b/board/rockchip/evb_rk3128/MAINTAINERS
new file mode 100644
index 0000000..f5145d1
--- /dev/null
+++ b/board/rockchip/evb_rk3128/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3128
+M: Kever Yang <kever.yang@rock-chips.com>
+S: Maintained
+F: board/rockchip/evb_rk3128
+F: include/configs/evb_rk3128.h
+F: configs/evb-rk3128_defconfig
diff --git a/board/rockchip/evb_rk3128/Makefile b/board/rockchip/evb_rk3128/Makefile
new file mode 100644
index 0000000..6040891
--- /dev/null
+++ b/board/rockchip/evb_rk3128/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evb-rk3128.o
diff --git a/board/rockchip/evb_rk3128/evb-rk3128.c b/board/rockchip/evb_rk3128/evb-rk3128.c
new file mode 100644
index 0000000..bf36e25
--- /dev/null
+++ b/board/rockchip/evb_rk3128/evb-rk3128.c
@@ -0,0 +1,9 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
diff --git a/include/configs/evb_rk3128.h b/include/configs/evb_rk3128.h
new file mode 100644
index 0000000..a34153a
--- /dev/null
+++ b/include/configs/evb_rk3128.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EVB_RK3128_H
+#define __EVB_RK3128_H
+
+#include <configs/rk3128_common.h>
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 6/7] rockchip: rk3128: add defconfig for evb-rk3128
2017-11-27 9:51 [U-Boot] [PATCH v2 0/7] rockchip: add new SoC support for RK3128 Kever Yang
` (4 preceding siblings ...)
2017-11-27 9:51 ` [U-Boot] [PATCH v2 5/7] rockchip: rk3128: add evb-rk3128 support Kever Yang
@ 2017-11-27 9:51 ` Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 7/7] rockchip: rk3128: add sdram driver Kever Yang
6 siblings, 2 replies; 21+ messages in thread
From: Kever Yang @ 2017-11-27 9:51 UTC (permalink / raw)
To: u-boot
Enable board config for evb-rk3128.
Serial output and eMMC works in this version.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2: None
configs/evb-rk3128_defconfig | 56 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 configs/evb-rk3128_defconfig
diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
new file mode 100644
index 0000000..7c2a607
--- /dev/null
+++ b/configs/evb-rk3128_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3128=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x60800800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RK3128=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_BASE=0x20068000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x310c
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y
--
1.9.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 7/7] rockchip: rk3128: add sdram driver
2017-11-27 9:51 [U-Boot] [PATCH v2 0/7] rockchip: add new SoC support for RK3128 Kever Yang
` (5 preceding siblings ...)
2017-11-27 9:51 ` [U-Boot] [PATCH v2 6/7] rockchip: rk3128: add defconfig for evb-rk3128 Kever Yang
@ 2017-11-27 9:51 ` Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot,v2,7/7] " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
6 siblings, 2 replies; 21+ messages in thread
From: Kever Yang @ 2017-11-27 9:51 UTC (permalink / raw)
To: u-boot
RK3128 support up to 2GB DDR3 sdram, one channel, 32bit data width.
This patch is only used for U-Boot, but not for SPL which will
comes later, maybe after we merge all the common code into a common
file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2: None
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3128.c | 59 +++++++++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram_rk3128.c
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 45b5fe7..1a1e557 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -5,6 +5,7 @@
#
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
+obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c
new file mode 100644
index 0000000..a33127f
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3128.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3128.h>
+#include <asm/arch/sdram_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct dram_info {
+ struct ram_info info;
+ struct rk3128_grf *grf;
+};
+
+static int rk3128_dmc_probe(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ debug("%s: grf=%p\n", __func__, priv->grf);
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = rockchip_sdram_size(
+ (phys_addr_t)&priv->grf->os_reg[1]);
+
+ return 0;
+}
+
+static int rk3128_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops rk3128_dmc_ops = {
+ .get_info = rk3128_dmc_get_info,
+};
+
+static const struct udevice_id rk3128_dmc_ids[] = {
+ { .compatible = "rockchip,rk3128-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(dmc_rk3128) = {
+ .name = "rockchip_rk3128_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3128_dmc_ids,
+ .ops = &rk3128_dmc_ops,
+ .probe = rk3128_dmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dram_info),
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot, v2, 1/7] rockchip: rk3128: add device tree file
2017-11-27 9:51 ` [U-Boot] [PATCH v2 1/7] rockchip: rk3128: add device tree file Kever Yang
@ 2017-11-27 19:17 ` Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 19:17 UTC (permalink / raw)
To: u-boot
> Add dts binding header for rk3128, files origin from kernel.
>
> Series-Changes: 2
> - fix i2c address
> - add saradc and usb phy node
> - emmc using fifo mode for there is no dma support in rk3128 emmc
> - add some clock id in cru.h
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2: None
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3128-evb.dts | 95 ++++
> arch/arm/dts/rk3128.dtsi | 804 +++++++++++++++++++++++++++++++++
> include/dt-bindings/clock/rk3128-cru.h | 190 ++++++++
> 4 files changed, 1090 insertions(+)
> create mode 100644 arch/arm/dts/rk3128-evb.dts
> create mode 100644 arch/arm/dts/rk3128.dtsi
> create mode 100644 include/dt-bindings/clock/rk3128-cru.h
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot, v2, 2/7] rockchip: rk3128: add soc basic support
2017-11-27 9:51 ` [U-Boot] [PATCH v2 2/7] rockchip: rk3128: add soc basic support Kever Yang
@ 2017-11-27 19:17 ` Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 19:17 UTC (permalink / raw)
To: u-boot
> RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU
> and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host
> and device, HDMI/LVDS/MIPI display.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - update setup_boot_mode() with master
> - enable board_late_init()
>
> arch/arm/mach-rockchip/Kconfig | 10 ++
> arch/arm/mach-rockchip/Makefile | 2 +
> arch/arm/mach-rockchip/rk3128-board.c | 127 ++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3128/Kconfig | 0
> arch/arm/mach-rockchip/rk3128/Makefile | 8 ++
> arch/arm/mach-rockchip/rk3128/rk3128.c | 12 +++
> arch/arm/mach-rockchip/rk3128/syscon_rk3128.c | 21 +++++
> include/configs/rk3128_common.h | 70 ++++++++++++++
> 8 files changed, 250 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3128-board.c
> create mode 100644 arch/arm/mach-rockchip/rk3128/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3128/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3128/rk3128.c
> create mode 100644 arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
> create mode 100644 include/configs/rk3128_common.h
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot,v2,3/7] rockchip: rk3128: add clock driver
2017-11-27 9:51 ` [U-Boot] [PATCH v2 3/7] rockchip: rk3128: add clock driver Kever Yang
@ 2017-11-27 19:17 ` Philipp Tomsich
0 siblings, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 19:17 UTC (permalink / raw)
To: u-boot
> Add rk3128 clock driver and cru structure definition.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - add clock for saradc, vop, nandc, i2c
> - update driver bind for sysreset driver and reset driver
> - add "rockchip,rk3126-cru" for compatible
>
> arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 212 +++++++++
> arch/arm/mach-rockchip/rk3128/Makefile | 1 +
> arch/arm/mach-rockchip/rk3128/clk_rk3128.c | 32 ++
> drivers/clk/rockchip/Makefile | 3 +-
> drivers/clk/rockchip/clk_rk3128.c | 609 ++++++++++++++++++++++++
> 5 files changed, 856 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3128.h
> create mode 100644 arch/arm/mach-rockchip/rk3128/clk_rk3128.c
> create mode 100644 drivers/clk/rockchip/clk_rk3128.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot,v2,7/7] rockchip: rk3128: add sdram driver
2017-11-27 9:51 ` [U-Boot] [PATCH v2 7/7] rockchip: rk3128: add sdram driver Kever Yang
@ 2017-11-27 19:17 ` Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 19:17 UTC (permalink / raw)
To: u-boot
> RK3128 support up to 2GB DDR3 sdram, one channel, 32bit data width.
>
> This patch is only used for U-Boot, but not for SPL which will
> comes later, maybe after we merge all the common code into a common
> file.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2: None
>
> drivers/ram/rockchip/Makefile | 1 +
> drivers/ram/rockchip/sdram_rk3128.c | 59 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 60 insertions(+)
> create mode 100644 drivers/ram/rockchip/sdram_rk3128.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot, v2, 6/7] rockchip: rk3128: add defconfig for evb-rk3128
2017-11-27 9:51 ` [U-Boot] [PATCH v2 6/7] rockchip: rk3128: add defconfig for evb-rk3128 Kever Yang
@ 2017-11-27 19:17 ` Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 19:17 UTC (permalink / raw)
To: u-boot
> Enable board config for evb-rk3128.
> Serial output and eMMC works in this version.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2: None
>
> configs/evb-rk3128_defconfig | 56 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
> create mode 100644 configs/evb-rk3128_defconfig
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot, v2, 5/7] rockchip: rk3128: add evb-rk3128 support
2017-11-27 9:51 ` [U-Boot] [PATCH v2 5/7] rockchip: rk3128: add evb-rk3128 support Kever Yang
@ 2017-11-27 19:17 ` Philipp Tomsich
2017-11-27 19:30 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 19:17 UTC (permalink / raw)
To: u-boot
> evb-rk3128 is an evb from Rockchip based on rk3128 SoC:
> - 2 USB2.0 Host port;
> - 1 HDMI port;
> - 2 10/100M eth port;
> - 2GB ddr;
> - 16GB eMMC;
> - UART to USB debug port;
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - enable usb nodes
>
> arch/arm/mach-rockchip/rk3128/Kconfig | 24 ++++++++++++++++++++++++
> board/rockchip/evb_rk3128/Kconfig | 15 +++++++++++++++
> board/rockchip/evb_rk3128/MAINTAINERS | 6 ++++++
> board/rockchip/evb_rk3128/Makefile | 7 +++++++
> board/rockchip/evb_rk3128/evb-rk3128.c | 9 +++++++++
> include/configs/evb_rk3128.h | 15 +++++++++++++++
> 6 files changed, 76 insertions(+)
> create mode 100644 board/rockchip/evb_rk3128/Kconfig
> create mode 100644 board/rockchip/evb_rk3128/MAINTAINERS
> create mode 100644 board/rockchip/evb_rk3128/Makefile
> create mode 100644 board/rockchip/evb_rk3128/evb-rk3128.c
> create mode 100644 include/configs/evb_rk3128.h
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot,v2,4/7] rockchip: rk3128: add pinctrl driver
2017-11-27 9:51 ` [U-Boot] [PATCH v2 4/7] rockchip: rk3128: add pinctrl driver Kever Yang
@ 2017-11-27 19:17 ` Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 19:17 UTC (permalink / raw)
To: u-boot
> Add rk3128 pinctrl driver and grf/iomux structure definition.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - remove debug info
> - update GPIO2C4/C5 SHIFT
>
> arch/arm/include/asm/arch-rockchip/grf_rk3128.h | 551 ++++++++++++++++++++++++
> drivers/pinctrl/Kconfig | 10 +
> drivers/pinctrl/rockchip/Makefile | 4 +-
> drivers/pinctrl/rockchip/pinctrl_rk3128.c | 187 ++++++++
> 4 files changed, 750 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3128.h
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot, v2, 5/7] rockchip: rk3128: add evb-rk3128 support
2017-11-27 9:51 ` [U-Boot] [PATCH v2 5/7] rockchip: rk3128: add evb-rk3128 support Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
@ 2017-11-27 19:30 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 19:30 UTC (permalink / raw)
To: u-boot
On Mon, 27 Nov 2017, Kever Yang wrote:
> evb-rk3128 is an evb from Rockchip based on rk3128 SoC:
> - 2 USB2.0 Host port;
> - 1 HDMI port;
> - 2 10/100M eth port;
> - 2GB ddr;
> - 16GB eMMC;
> - UART to USB debug port;
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
See below for requested changes.
> ---
>
> Changes in v2:
> - enable usb nodes
>
> arch/arm/mach-rockchip/rk3128/Kconfig | 24 ++++++++++++++++++++++++
> board/rockchip/evb_rk3128/Kconfig | 15 +++++++++++++++
> board/rockchip/evb_rk3128/MAINTAINERS | 6 ++++++
> board/rockchip/evb_rk3128/Makefile | 7 +++++++
> board/rockchip/evb_rk3128/evb-rk3128.c | 9 +++++++++
> include/configs/evb_rk3128.h | 15 +++++++++++++++
> 6 files changed, 76 insertions(+)
> create mode 100644 board/rockchip/evb_rk3128/Kconfig
> create mode 100644 board/rockchip/evb_rk3128/MAINTAINERS
> create mode 100644 board/rockchip/evb_rk3128/Makefile
> create mode 100644 board/rockchip/evb_rk3128/evb-rk3128.c
> create mode 100644 include/configs/evb_rk3128.h
>
> diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig
> index e69de29..40655a2 100644
> --- a/arch/arm/mach-rockchip/rk3128/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3128/Kconfig
> @@ -0,0 +1,24 @@
> +if ROCKCHIP_RK3128
> +
> +choice
> + prompt "RK3128 board select"
> +
> +config TARGET_EVB_RK3128
> + bool "RK3128 evaluation board"
> + select BOARD_LATE_INIT
> + help
> + RK3128evb is a evaluation board for Rockchip rk3128,
> + with full function and phisical connectors support like
> + usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
> +
> +endchoice
> +
> +config SYS_SOC
> + default "rockchip"
> +
> +config SYS_MALLOC_F_LEN
> + default 0x0800
> +
> +source "board/rockchip/evb_rk3128/Kconfig"
> +
> +endif
> diff --git a/board/rockchip/evb_rk3128/Kconfig b/board/rockchip/evb_rk3128/Kconfig
> new file mode 100644
> index 0000000..5b3095a
> --- /dev/null
> +++ b/board/rockchip/evb_rk3128/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_EVB_RK3128
> +
> +config SYS_BOARD
> + default "evb_rk3128"
> +
> +config SYS_VENDOR
> + default "rockchip"
> +
> +config SYS_CONFIG_NAME
> + default "evb_rk3128"
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> + def_bool y
> +
> +endif
> diff --git a/board/rockchip/evb_rk3128/MAINTAINERS b/board/rockchip/evb_rk3128/MAINTAINERS
> new file mode 100644
> index 0000000..f5145d1
> --- /dev/null
> +++ b/board/rockchip/evb_rk3128/MAINTAINERS
> @@ -0,0 +1,6 @@
> +EVB-RK3128
> +M: Kever Yang <kever.yang@rock-chips.com>
> +S: Maintained
> +F: board/rockchip/evb_rk3128
> +F: include/configs/evb_rk3128.h
> +F: configs/evb-rk3128_defconfig
> diff --git a/board/rockchip/evb_rk3128/Makefile b/board/rockchip/evb_rk3128/Makefile
> new file mode 100644
> index 0000000..6040891
> --- /dev/null
> +++ b/board/rockchip/evb_rk3128/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# (C) Copyright 2017 Rockchip Electronics Co., Ltd
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += evb-rk3128.o
> diff --git a/board/rockchip/evb_rk3128/evb-rk3128.c b/board/rockchip/evb_rk3128/evb-rk3128.c
> new file mode 100644
> index 0000000..bf36e25
> --- /dev/null
> +++ b/board/rockchip/evb_rk3128/evb-rk3128.c
> @@ -0,0 +1,9 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
If this file is (essentially) empty, there is no point in having it.
And once this one gets removed, the 'obj-y +=' in the Makefile should also
be changed respectively.
> diff --git a/include/configs/evb_rk3128.h b/include/configs/evb_rk3128.h
> new file mode 100644
> index 0000000..a34153a
> --- /dev/null
> +++ b/include/configs/evb_rk3128.h
> @@ -0,0 +1,15 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __EVB_RK3128_H
> +#define __EVB_RK3128_H
> +
> +#include <configs/rk3128_common.h>
> +
> +#define CONFIG_ENV_IS_IN_MMC
This has been migrated to Kconfig, please use the defconfig for this.
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +
> +#endif
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot, v2, 1/7] rockchip: rk3128: add device tree file
2017-11-27 9:51 ` [U-Boot] [PATCH v2 1/7] rockchip: rk3128: add device tree file Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
@ 2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 20:28 UTC (permalink / raw)
To: u-boot
> Add dts binding header for rk3128, files origin from kernel.
>
> Series-Changes: 2
> - fix i2c address
> - add saradc and usb phy node
> - emmc using fifo mode for there is no dma support in rk3128 emmc
> - add some clock id in cru.h
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3128-evb.dts | 95 ++++
> arch/arm/dts/rk3128.dtsi | 804 +++++++++++++++++++++++++++++++++
> include/dt-bindings/clock/rk3128-cru.h | 190 ++++++++
> 4 files changed, 1090 insertions(+)
> create mode 100644 arch/arm/dts/rk3128-evb.dts
> create mode 100644 arch/arm/dts/rk3128.dtsi
> create mode 100644 include/dt-bindings/clock/rk3128-cru.h
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot, v2, 6/7] rockchip: rk3128: add defconfig for evb-rk3128
2017-11-27 9:51 ` [U-Boot] [PATCH v2 6/7] rockchip: rk3128: add defconfig for evb-rk3128 Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
@ 2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 20:28 UTC (permalink / raw)
To: u-boot
> Enable board config for evb-rk3128.
> Serial output and eMMC works in this version.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
> configs/evb-rk3128_defconfig | 56 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
> create mode 100644 configs/evb-rk3128_defconfig
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot,v2,7/7] rockchip: rk3128: add sdram driver
2017-11-27 9:51 ` [U-Boot] [PATCH v2 7/7] rockchip: rk3128: add sdram driver Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot,v2,7/7] " Philipp Tomsich
@ 2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 20:28 UTC (permalink / raw)
To: u-boot
> RK3128 support up to 2GB DDR3 sdram, one channel, 32bit data width.
>
> This patch is only used for U-Boot, but not for SPL which will
> comes later, maybe after we merge all the common code into a common
> file.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
> drivers/ram/rockchip/Makefile | 1 +
> drivers/ram/rockchip/sdram_rk3128.c | 59 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 60 insertions(+)
> create mode 100644 drivers/ram/rockchip/sdram_rk3128.c
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot,v2,4/7] rockchip: rk3128: add pinctrl driver
2017-11-27 9:51 ` [U-Boot] [PATCH v2 4/7] rockchip: rk3128: add pinctrl driver Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot,v2,4/7] " Philipp Tomsich
@ 2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 20:28 UTC (permalink / raw)
To: u-boot
> Add rk3128 pinctrl driver and grf/iomux structure definition.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2:
> - remove debug info
> - update GPIO2C4/C5 SHIFT
>
> arch/arm/include/asm/arch-rockchip/grf_rk3128.h | 551 ++++++++++++++++++++++++
> drivers/pinctrl/Kconfig | 10 +
> drivers/pinctrl/rockchip/Makefile | 4 +-
> drivers/pinctrl/rockchip/pinctrl_rk3128.c | 187 ++++++++
> 4 files changed, 750 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3128.h
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [U-Boot, v2, 2/7] rockchip: rk3128: add soc basic support
2017-11-27 9:51 ` [U-Boot] [PATCH v2 2/7] rockchip: rk3128: add soc basic support Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
@ 2017-11-27 20:28 ` Philipp Tomsich
1 sibling, 0 replies; 21+ messages in thread
From: Philipp Tomsich @ 2017-11-27 20:28 UTC (permalink / raw)
To: u-boot
> RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU
> and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host
> and device, HDMI/LVDS/MIPI display.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2:
> - update setup_boot_mode() with master
> - enable board_late_init()
>
> arch/arm/mach-rockchip/Kconfig | 10 ++
> arch/arm/mach-rockchip/Makefile | 2 +
> arch/arm/mach-rockchip/rk3128-board.c | 127 ++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3128/Kconfig | 0
> arch/arm/mach-rockchip/rk3128/Makefile | 8 ++
> arch/arm/mach-rockchip/rk3128/rk3128.c | 12 +++
> arch/arm/mach-rockchip/rk3128/syscon_rk3128.c | 21 +++++
> include/configs/rk3128_common.h | 70 ++++++++++++++
> 8 files changed, 250 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3128-board.c
> create mode 100644 arch/arm/mach-rockchip/rk3128/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3128/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3128/rk3128.c
> create mode 100644 arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
> create mode 100644 include/configs/rk3128_common.h
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2017-11-27 20:28 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-27 9:51 [U-Boot] [PATCH v2 0/7] rockchip: add new SoC support for RK3128 Kever Yang
2017-11-27 9:51 ` [U-Boot] [PATCH v2 1/7] rockchip: rk3128: add device tree file Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 2/7] rockchip: rk3128: add soc basic support Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 3/7] rockchip: rk3128: add clock driver Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot,v2,3/7] " Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 4/7] rockchip: rk3128: add pinctrl driver Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot,v2,4/7] " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 5/7] rockchip: rk3128: add evb-rk3128 support Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-27 19:30 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 6/7] rockchip: rk3128: add defconfig for evb-rk3128 Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
2017-11-27 9:51 ` [U-Boot] [PATCH v2 7/7] rockchip: rk3128: add sdram driver Kever Yang
2017-11-27 19:17 ` [U-Boot] [U-Boot,v2,7/7] " Philipp Tomsich
2017-11-27 20:28 ` Philipp Tomsich
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