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Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH 19/25] drm/msm/dpu: don't use unsupported blend stages Content-Language: en-US To: Dmitry Baryshkov , Bjorn Andersson , Rob Clark , Sean Paul References: <20220209172520.3719906-1-dmitry.baryshkov@linaro.org> <20220209172520.3719906-20-dmitry.baryshkov@linaro.org> From: Abhinav Kumar In-Reply-To: <20220209172520.3719906-20-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2/9/2022 9:25 AM, Dmitry Baryshkov wrote: > The atomic_check compares blending stage with DPU_STAGE_MAX (maximum > amount of blending stages supported by the driver), however we should > compare it against .max_mixer_blendstages, the maximum blend stage > supported by the mixer. > > Signed-off-by: Dmitry Baryshkov This seems reasonable to me, Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index 637d164667e9..952ff11162c0 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -927,9 +927,9 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, > pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; > > pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; > - if (pstate->stage >= DPU_STAGE_MAX) { > + if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { > DPU_ERROR("> %d plane stages assigned\n", > - DPU_STAGE_MAX - DPU_STAGE_0); > + pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); > return -EINVAL; > } > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C81F0C433F5 for ; Sat, 14 May 2022 02:56:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231571AbiENC40 (ORCPT ); Fri, 13 May 2022 22:56:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231899AbiENC4R (ORCPT ); Fri, 13 May 2022 22:56:17 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AD52CEB9A for ; Fri, 13 May 2022 18:57:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652493476; x=1684029476; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=DDwU0MIIX7cHAeGzIXm3PASsFEXV/dXGCnlifbLzn+E=; b=jjRHBy/8sSuv9EF0M5/fQ3vdPxRKqjddbqZcE6JRVftvuQsC+onlL0tM Onu08EPMBAnbGil0BS5vdgM8gufz5sddRzMFW73eqd7aS7vRN6HXjfPsa FTcsjboIPqdXto9Ud3w7N5ARzcvkEkERFsADmu7G/gdkEjE14DlmIpxXV 4=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 13 May 2022 18:57:56 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2022 18:57:55 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 13 May 2022 18:57:55 -0700 Received: from [10.38.247.112] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 13 May 2022 18:57:53 -0700 Message-ID: Date: Fri, 13 May 2022 18:57:51 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH 19/25] drm/msm/dpu: don't use unsupported blend stages Content-Language: en-US To: Dmitry Baryshkov , Bjorn Andersson , Rob Clark , Sean Paul CC: Stephen Boyd , David Airlie , Daniel Vetter , , , References: <20220209172520.3719906-1-dmitry.baryshkov@linaro.org> <20220209172520.3719906-20-dmitry.baryshkov@linaro.org> From: Abhinav Kumar In-Reply-To: <20220209172520.3719906-20-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2/9/2022 9:25 AM, Dmitry Baryshkov wrote: > The atomic_check compares blending stage with DPU_STAGE_MAX (maximum > amount of blending stages supported by the driver), however we should > compare it against .max_mixer_blendstages, the maximum blend stage > supported by the mixer. > > Signed-off-by: Dmitry Baryshkov This seems reasonable to me, Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index 637d164667e9..952ff11162c0 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -927,9 +927,9 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, > pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; > > pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; > - if (pstate->stage >= DPU_STAGE_MAX) { > + if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { > DPU_ERROR("> %d plane stages assigned\n", > - DPU_STAGE_MAX - DPU_STAGE_0); > + pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); > return -EINVAL; > } >