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From: Jan Beulich <jbeulich@suse.com>
To: Igor Druzhinin <igor.druzhinin@citrix.com>
Cc: andrew.cooper3@citrix.com, roger.pau@citrix.com, wl@xen.org,
	jun.nakajima@intel.com, kevin.tian@intel.com,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3] x86/intel: insert Ice Lake-X (server) and Ice Lake-D model numbers
Date: Wed, 6 Jan 2021 12:04:45 +0100	[thread overview]
Message-ID: <b0c7ccb7-32b8-a022-72ad-274e0a0c6dca@suse.com> (raw)
In-Reply-To: <1608755520-1277-1-git-send-email-igor.druzhinin@citrix.com>

On 23.12.2020 21:32, Igor Druzhinin wrote:
> LBR, C-state MSRs should correspond to Ice Lake desktop according to
> External Design Specification vol.2 for both models.
> 
> Ice Lake-X is known to expose IF_PSCHANGE_MC_NO in IA32_ARCH_CAPABILITIES MSR
> (confirmed on Whitley SDP) which means the erratum is fixed in hardware for
> that model and therefore it shouldn't be present in has_if_pschange_mc list.
> Provisionally assume the same to be the case for Ice Lake-D.

I did find Ice Lake D EDS, and it confirms the respective additions.
In the course I also found the "plain" Ice Lake EDS, and it seems to
contradict SDM vol 4 in that it doesn't list CC3_RESIDENCY (0x3FC).
For now I guess we can consider this a doc error.

I didn't find Ice Lake-X EDS, though.

Jan


  reply	other threads:[~2021-01-06 11:05 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-23 20:32 [PATCH v3] x86/intel: insert Ice Lake-X (server) and Ice Lake-D model numbers Igor Druzhinin
2021-01-06 11:04 ` Jan Beulich [this message]
2021-01-07  2:17   ` Igor Druzhinin
2021-01-08 10:03     ` Jan Beulich
2021-01-27  9:52 ` Andrew Cooper
2021-04-08 12:41   ` Igor Druzhinin

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