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[83.57.170.138]) by smtp.gmail.com with ESMTPSA id di20sm7630018edb.26.2020.07.17.00.59.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Jul 2020 00:59:22 -0700 (PDT) Subject: Re: [PATCH v6 01/13] hw/misc: Add NPCM7xx System Global Control Registers device model To: Havard Skinnemoen , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20200717060258.1602319-1-hskinnemoen@google.com> <20200717060258.1602319-2-hskinnemoen@google.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Fri, 17 Jul 2020 09:59:20 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200717060258.1602319-2-hskinnemoen@google.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::642; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kfting@nuvoton.com, =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Avi.Fishman@nuvoton.com, Joel Stanley Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/17/20 8:02 AM, Havard Skinnemoen wrote: > Implement a device model for the System Global Control Registers in the > NPCM730 and NPCM750 BMC SoCs. > > This is primarily used to enable SMP boot (the boot ROM spins reading > the SCRPAD register) and DDR memory initialization; other registers are > best effort for now. > > The reset values of the MDLR and PWRON registers are determined by the > SoC variant (730 vs 750) and board straps respectively. > > Reviewed-by: Joel Stanley > Reviewed-by: Cédric Le Goater > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Havard Skinnemoen > --- > include/hw/misc/npcm7xx_gcr.h | 76 ++++++++++++ > hw/misc/npcm7xx_gcr.c | 227 ++++++++++++++++++++++++++++++++++ > MAINTAINERS | 8 ++ > hw/arm/Kconfig | 3 + > hw/misc/Makefile.objs | 1 + > hw/misc/trace-events | 4 + > 6 files changed, 319 insertions(+) > create mode 100644 include/hw/misc/npcm7xx_gcr.h > create mode 100644 hw/misc/npcm7xx_gcr.c ... > +static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp) > +{ > + ERRP_GUARD(); > + NPCM7xxGCRState *s = NPCM7XX_GCR(dev); > + uint64_t dram_size; > + Object *obj; > + > + obj = object_property_get_link(OBJECT(dev), "dram-mr", errp); > + if (!obj) { > + error_prepend(errp, "%s: required dram-mr link not found: ", __func__); > + return; > + } > + dram_size = memory_region_size(MEMORY_REGION(obj)); > + if (!is_power_of_2(dram_size) || > + dram_size < NPCM7XX_GCR_MIN_DRAM_SIZE || > + dram_size > NPCM7XX_GCR_MAX_DRAM_SIZE) { > + error_setg(errp, "%s: unsupported DRAM size %" PRIu64, > + __func__, dram_size); Nitpicking if you ever have to respin, please use size_to_str() here, > + error_append_hint(errp, > + "DRAM size must be a power of two between %" PRIu64 > + " and %" PRIu64 " MiB, inclusive.\n", > + NPCM7XX_GCR_MIN_DRAM_SIZE / MiB, > + NPCM7XX_GCR_MAX_DRAM_SIZE / MiB); and here. > + return; > + } > + > + /* Power-on reset value */ > + s->reset_intcr3 = 0x00001002; > + > + /* > + * The GMMAP (Graphics Memory Map) field is used by u-boot to detect the > + * DRAM size, and is normally initialized by the boot block as part of DRAM > + * training. However, since we don't have a complete emulation of the > + * memory controller and try to make it look like it has already been > + * initialized, the boot block will skip this initialization, and we need > + * to make sure this field is set correctly up front. > + * > + * WARNING: some versions of u-boot only looks at bits 8 and 9, so 2 GiB of > + * DRAM will be interpreted as 128 MiB. > + * > + * https://github.com/Nuvoton-Israel/u-boot/blob/2aef993bd2aafeb5408dbaad0f3ce099ee40c4aa/board/nuvoton/poleg/poleg.c#L244 > + */ > + s->reset_intcr3 |= ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8; Nice :) > +} [...]