Hi Sergei
Thanks for your comment.
>> + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST )
>
> Parens not needed and the spaces after/before them even less so.
>
OK
I will update in V2
Thanks & best regards.
Bui Duc Phuc
Hi Sergei
Thanks for your comment.
>> + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST )
>
> Parens not needed and the spaces after/before them even less so.
>
OK
I will update in V2
Thanks & best regards.
Bui Duc Phuc
Hi Sergei
Thanks for your comment.
>> + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST )
>
> Parens not needed and the spaces after/before them even less so.
>
OK
I will update in V2
Thanks & best regards.
Bui Duc Phuc
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Hi, These are my first patches which will be added CMT driver for support R-car Gen3 series (r8a7795 and r8a7796). Please consider these patches. Best regards. Bui Duc Phuc (8): devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings ARM64: dts: r8a7795: Add CMT device to DT ARM64: dts: r8a7796: Add CMT device to DT clk: renesas: r8a7795: Add CMT clocks clk: renesas: r8a7796: Add CMT clocks clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1 clocksource: Kconfig: Modify CMT config support 64bit ARM64: defconfig: Enable SH_TIMER_CMT config option .../devicetree/bindings/timer/renesas,cmt.txt | 2 ++ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 +++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 +++ drivers/clocksource/Kconfig | 2 +- drivers/clocksource/sh_cmt.c | 21 +++++++++++++-- 8 files changed, 91 insertions(+), 3 deletions(-) -- 2.7.4
From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> Hi, These are my first patches which will be added CMT driver for support R-car Gen3 series (r8a7795 and r8a7796). Please consider these patches. Best regards. Bui Duc Phuc (8): devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings ARM64: dts: r8a7795: Add CMT device to DT ARM64: dts: r8a7796: Add CMT device to DT clk: renesas: r8a7795: Add CMT clocks clk: renesas: r8a7796: Add CMT clocks clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1 clocksource: Kconfig: Modify CMT config support 64bit ARM64: defconfig: Enable SH_TIMER_CMT config option .../devicetree/bindings/timer/renesas,cmt.txt | 2 ++ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 +++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 +++ drivers/clocksource/Kconfig | 2 +- drivers/clocksource/sh_cmt.c | 21 +++++++++++++-- 8 files changed, 91 insertions(+), 3 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Hi, These are my first patches which will be added CMT driver for support R-car Gen3 series (r8a7795 and r8a7796). Please consider these patches. Best regards. Bui Duc Phuc (8): devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings ARM64: dts: r8a7795: Add CMT device to DT ARM64: dts: r8a7796: Add CMT device to DT clk: renesas: r8a7795: Add CMT clocks clk: renesas: r8a7796: Add CMT clocks clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1 clocksource: Kconfig: Modify CMT config support 64bit ARM64: defconfig: Enable SH_TIMER_CMT config option .../devicetree/bindings/timer/renesas,cmt.txt | 2 ++ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 +++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 +++ drivers/clocksource/Kconfig | 2 +- drivers/clocksource/sh_cmt.c | 21 +++++++++++++-- 8 files changed, 91 insertions(+), 3 deletions(-) -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Hi, These are my first patches which will be added CMT driver for support R-car Gen3 series (r8a7795 and r8a7796). Please consider these patches. Best regards. Bui Duc Phuc (8): devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings ARM64: dts: r8a7795: Add CMT device to DT ARM64: dts: r8a7796: Add CMT device to DT clk: renesas: r8a7795: Add CMT clocks clk: renesas: r8a7796: Add CMT clocks clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1 clocksource: Kconfig: Modify CMT config support 64bit ARM64: defconfig: Enable SH_TIMER_CMT config option .../devicetree/bindings/timer/renesas,cmt.txt | 2 ++ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 +++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 +++ drivers/clocksource/Kconfig | 2 +- drivers/clocksource/sh_cmt.c | 21 +++++++++++++-- 8 files changed, 91 insertions(+), 3 deletions(-) -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add documentation for new separate CMT0 and CMT1 DT compatible strings for R-Car Gen3. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 1a05c1b..72fd526 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -52,6 +52,8 @@ Required Properties: (CMT[01] on r8a73a4, r8a7790 and r8a7791) This is a fallback for the renesas,cmt-48-r8a73a4, renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. + - "renesas,cmt-48-gen3" for third generation 48-bit CMT + (CMT[01] on r8a7795 and r8a7796) - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel. -- 2.7.4
From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> Add documentation for new separate CMT0 and CMT1 DT compatible strings for R-Car Gen3. Signed-off-by: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 1a05c1b..72fd526 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -52,6 +52,8 @@ Required Properties: (CMT[01] on r8a73a4, r8a7790 and r8a7791) This is a fallback for the renesas,cmt-48-r8a73a4, renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. + - "renesas,cmt-48-gen3" for third generation 48-bit CMT + (CMT[01] on r8a7795 and r8a7796) - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel. -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add documentation for new separate CMT0 and CMT1 DT compatible strings for R-Car Gen3. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 1a05c1b..72fd526 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -52,6 +52,8 @@ Required Properties: (CMT[01] on r8a73a4, r8a7790 and r8a7791) This is a fallback for the renesas,cmt-48-r8a73a4, renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. + - "renesas,cmt-48-gen3" for third generation 48-bit CMT + (CMT[01] on r8a7795 and r8a7796) - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel. -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add documentation for new separate CMT0 and CMT1 DT compatible strings for R-Car Gen3. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 1a05c1b..72fd526 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -52,6 +52,8 @@ Required Properties: (CMT[01] on r8a73a4, r8a7790 and r8a7791) This is a fallback for the renesas,cmt-48-r8a73a4, renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. + - "renesas,cmt-48-gen3" for third generation 48-bit CMT + (CMT[01] on r8a7795 and r8a7796) - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel. -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add the CMT0 and CMT1 counters to the r8a7795 device tree Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b902356..2333830 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -312,6 +312,36 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- 2.7.4
From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> Add the CMT0 and CMT1 counters to the r8a7795 device tree Signed-off-by: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b902356..2333830 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -312,6 +312,36 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add the CMT0 and CMT1 counters to the r8a7795 device tree Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b902356..2333830 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -312,6 +312,36 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add the CMT0 and CMT1 counters to the r8a7795 device tree Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b902356..2333830 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -312,6 +312,36 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer at e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer at e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + cpg: clock-controller at e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add the CMT0 and CMT1 counters to the r8a7796 device tree Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 1edf824..6f5ce3f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -98,6 +98,36 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + wdt0: watchdog@e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; -- 2.7.4
From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> Add the CMT0 and CMT1 counters to the r8a7796 device tree Signed-off-by: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 1edf824..6f5ce3f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -98,6 +98,36 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + wdt0: watchdog@e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add the CMT0 and CMT1 counters to the r8a7796 device tree Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 1edf824..6f5ce3f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -98,6 +98,36 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + wdt0: watchdog@e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add the CMT0 and CMT1 counters to the r8a7796 device tree Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 1edf824..6f5ce3f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -98,6 +98,36 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer at e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer at e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + wdt0: watchdog at e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> This patch adds CMT module clocks for r8a7795 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index e38bf60..86968ea 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -123,6 +123,10 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1), + DEF_MOD("cmt3", 300, R8A7795_CLK_R), + DEF_MOD("cmt2", 301, R8A7795_CLK_R), + DEF_MOD("cmt1", 302, R8A7795_CLK_R), + DEF_MOD("cmt0", 303, R8A7795_CLK_R), DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), -- 2.7.4
From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> This patch adds CMT module clocks for r8a7795 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> --- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index e38bf60..86968ea 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -123,6 +123,10 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1), + DEF_MOD("cmt3", 300, R8A7795_CLK_R), + DEF_MOD("cmt2", 301, R8A7795_CLK_R), + DEF_MOD("cmt1", 302, R8A7795_CLK_R), + DEF_MOD("cmt0", 303, R8A7795_CLK_R), DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> This patch adds CMT module clocks for r8a7795 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index e38bf60..86968ea 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -123,6 +123,10 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1), + DEF_MOD("cmt3", 300, R8A7795_CLK_R), + DEF_MOD("cmt2", 301, R8A7795_CLK_R), + DEF_MOD("cmt1", 302, R8A7795_CLK_R), + DEF_MOD("cmt0", 303, R8A7795_CLK_R), DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> This patch adds CMT module clocks for r8a7795 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index e38bf60..86968ea 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -123,6 +123,10 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1), + DEF_MOD("cmt3", 300, R8A7795_CLK_R), + DEF_MOD("cmt2", 301, R8A7795_CLK_R), + DEF_MOD("cmt1", 302, R8A7795_CLK_R), + DEF_MOD("cmt0", 303, R8A7795_CLK_R), DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> This patch adds CMT module clocks for r8a7796 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index c84b549..63607bb 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { + DEF_MOD("cmt3", 300, R8A7796_CLK_R), + DEF_MOD("cmt2", 301, R8A7796_CLK_R), + DEF_MOD("cmt1", 302, R8A7796_CLK_R), + DEF_MOD("cmt0", 303, R8A7796_CLK_R), DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), }; -- 2.7.4
From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> This patch adds CMT module clocks for r8a7796 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index c84b549..63607bb 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { + DEF_MOD("cmt3", 300, R8A7796_CLK_R), + DEF_MOD("cmt2", 301, R8A7796_CLK_R), + DEF_MOD("cmt1", 302, R8A7796_CLK_R), + DEF_MOD("cmt0", 303, R8A7796_CLK_R), DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), }; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> This patch adds CMT module clocks for r8a7796 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index c84b549..63607bb 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { + DEF_MOD("cmt3", 300, R8A7796_CLK_R), + DEF_MOD("cmt2", 301, R8A7796_CLK_R), + DEF_MOD("cmt1", 302, R8A7796_CLK_R), + DEF_MOD("cmt0", 303, R8A7796_CLK_R), DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), }; -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> This patch adds CMT module clocks for r8a7796 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index c84b549..63607bb 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { + DEF_MOD("cmt3", 300, R8A7796_CLK_R), + DEF_MOD("cmt2", 301, R8A7796_CLK_R), + DEF_MOD("cmt1", 302, R8A7796_CLK_R), + DEF_MOD("cmt0", 303, R8A7796_CLK_R), DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), }; -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 103c493..1542aef 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -69,6 +69,7 @@ enum sh_cmt_model { SH_CMT_32BIT_FAST, SH_CMT_48BIT, SH_CMT_48BIT_GEN2, + SH_CMT_48BIT_GEN3, }; struct sh_cmt_info { @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, + [SH_CMT_48BIT_GEN3] = { + .model = SH_CMT_48BIT_GEN3, + .width = 32, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), + .read_control = sh_cmt_read32, + .write_control = sh_cmt_write32, + .read_count = sh_cmt_read32, + .write_count = sh_cmt_write32, + }, }; #define CMCSR 0 /* channel register */ @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->cmt = cmt; ch->index = index; ch->hwidx = hwidx; + ch->timer_bit = hwidx; /* * Compute the address of the channel control register block. For the @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, case SH_CMT_48BIT_GEN2: ch->iostart = cmt->mapbase + ch->hwidx * 0x100; ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; + break; + case SH_CMT_48BIT_GEN3: + ch->iostart = cmt->mapbase + ch->hwidx * 0x100; + ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; break; } @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->match_value = ch->max_match_value; raw_spin_lock_init(&ch->lock); - ch->timer_bit = cmt->info->model = SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; - ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), clockevent, clocksource); if (ret) { @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, + { .compatible = "renesas,cmt-48-gen3", .data = &sh_cmt_info[SH_CMT_48BIT_GEN3] }, { } }; MODULE_DEVICE_TABLE(of, sh_cmt_of_table); -- 2.7.4
From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. Signed-off-by: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> --- drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 103c493..1542aef 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -69,6 +69,7 @@ enum sh_cmt_model { SH_CMT_32BIT_FAST, SH_CMT_48BIT, SH_CMT_48BIT_GEN2, + SH_CMT_48BIT_GEN3, }; struct sh_cmt_info { @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, + [SH_CMT_48BIT_GEN3] = { + .model = SH_CMT_48BIT_GEN3, + .width = 32, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), + .read_control = sh_cmt_read32, + .write_control = sh_cmt_write32, + .read_count = sh_cmt_read32, + .write_count = sh_cmt_write32, + }, }; #define CMCSR 0 /* channel register */ @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->cmt = cmt; ch->index = index; ch->hwidx = hwidx; + ch->timer_bit = hwidx; /* * Compute the address of the channel control register block. For the @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, case SH_CMT_48BIT_GEN2: ch->iostart = cmt->mapbase + ch->hwidx * 0x100; ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; + break; + case SH_CMT_48BIT_GEN3: + ch->iostart = cmt->mapbase + ch->hwidx * 0x100; + ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; break; } @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->match_value = ch->max_match_value; raw_spin_lock_init(&ch->lock); - ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; - ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), clockevent, clocksource); if (ret) { @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, + { .compatible = "renesas,cmt-48-gen3", .data = &sh_cmt_info[SH_CMT_48BIT_GEN3] }, { } }; MODULE_DEVICE_TABLE(of, sh_cmt_of_table); -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 103c493..1542aef 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -69,6 +69,7 @@ enum sh_cmt_model { SH_CMT_32BIT_FAST, SH_CMT_48BIT, SH_CMT_48BIT_GEN2, + SH_CMT_48BIT_GEN3, }; struct sh_cmt_info { @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, + [SH_CMT_48BIT_GEN3] = { + .model = SH_CMT_48BIT_GEN3, + .width = 32, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), + .read_control = sh_cmt_read32, + .write_control = sh_cmt_write32, + .read_count = sh_cmt_read32, + .write_count = sh_cmt_write32, + }, }; #define CMCSR 0 /* channel register */ @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->cmt = cmt; ch->index = index; ch->hwidx = hwidx; + ch->timer_bit = hwidx; /* * Compute the address of the channel control register block. For the @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, case SH_CMT_48BIT_GEN2: ch->iostart = cmt->mapbase + ch->hwidx * 0x100; ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; + break; + case SH_CMT_48BIT_GEN3: + ch->iostart = cmt->mapbase + ch->hwidx * 0x100; + ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; break; } @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->match_value = ch->max_match_value; raw_spin_lock_init(&ch->lock); - ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; - ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), clockevent, clocksource); if (ret) { @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, + { .compatible = "renesas,cmt-48-gen3", .data = &sh_cmt_info[SH_CMT_48BIT_GEN3] }, { } }; MODULE_DEVICE_TABLE(of, sh_cmt_of_table); -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 103c493..1542aef 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -69,6 +69,7 @@ enum sh_cmt_model { SH_CMT_32BIT_FAST, SH_CMT_48BIT, SH_CMT_48BIT_GEN2, + SH_CMT_48BIT_GEN3, }; struct sh_cmt_info { @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, + [SH_CMT_48BIT_GEN3] = { + .model = SH_CMT_48BIT_GEN3, + .width = 32, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), + .read_control = sh_cmt_read32, + .write_control = sh_cmt_write32, + .read_count = sh_cmt_read32, + .write_count = sh_cmt_write32, + }, }; #define CMCSR 0 /* channel register */ @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->cmt = cmt; ch->index = index; ch->hwidx = hwidx; + ch->timer_bit = hwidx; /* * Compute the address of the channel control register block. For the @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, case SH_CMT_48BIT_GEN2: ch->iostart = cmt->mapbase + ch->hwidx * 0x100; ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; + break; + case SH_CMT_48BIT_GEN3: + ch->iostart = cmt->mapbase + ch->hwidx * 0x100; + ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; break; } @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->match_value = ch->max_match_value; raw_spin_lock_init(&ch->lock); - ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; - ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), clockevent, clocksource); if (ret) { @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, + { .compatible = "renesas,cmt-48-gen3", .data = &sh_cmt_info[SH_CMT_48BIT_GEN3] }, { } }; MODULE_DEVICE_TABLE(of, sh_cmt_of_table); -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Modify CMT config to support 64bit Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 5677886..62c2bcb 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI bool config SH_TIMER_CMT - bool "Renesas CMT timer driver" if COMPILE_TEST + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM default SYS_SUPPORTS_SH_CMT -- 2.7.4
From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> Modify CMT config to support 64bit Signed-off-by: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 5677886..62c2bcb 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI bool config SH_TIMER_CMT - bool "Renesas CMT timer driver" if COMPILE_TEST + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM default SYS_SUPPORTS_SH_CMT -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Modify CMT config to support 64bit Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 5677886..62c2bcb 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI bool config SH_TIMER_CMT - bool "Renesas CMT timer driver" if COMPILE_TEST + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM default SYS_SUPPORTS_SH_CMT -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Modify CMT config to support 64bit Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 5677886..62c2bcb 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI bool config SH_TIMER_CMT - bool "Renesas CMT timer driver" if COMPILE_TEST + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM default SYS_SUPPORTS_SH_CMT -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Enable SH CMT driver for R-car Gen3 : SH_TIMER_CMT Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index eadf485..72f892d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -3,6 +3,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SH_TIMER_CMT=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y -- 2.7.4
From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> Enable SH CMT driver for R-car Gen3 : SH_TIMER_CMT Signed-off-by: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index eadf485..72f892d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -3,6 +3,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SH_TIMER_CMT=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Enable SH CMT driver for R-car Gen3 : SH_TIMER_CMT Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index eadf485..72f892d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -3,6 +3,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SH_TIMER_CMT=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y -- 2.7.4
From: Bui Duc Phuc <bd-phuc@jinso.co.jp> Enable SH CMT driver for R-car Gen3 : SH_TIMER_CMT Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index eadf485..72f892d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -3,6 +3,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SH_TIMER_CMT=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y -- 2.7.4
On 9/9/2016 2:43 PM, bd-phuc@jinso.co.jp wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
>
> Modify CMT config to support 64bit
>
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
> ---
> drivers/clocksource/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 5677886..62c2bcb 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI
> bool
>
> config SH_TIMER_CMT
> - bool "Renesas CMT timer driver" if COMPILE_TEST
> + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST )
Parens not needed and the spaces after/before them even less so.
[...]
MBR, Sergei
On 9/9/2016 2:43 PM, bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org wrote: > From: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> > > Modify CMT config to support 64bit > > Signed-off-by: Bui Duc Phuc <bd-phuc-HEF513clHfp3+QwDJ9on6Q@public.gmane.org> > --- > drivers/clocksource/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 5677886..62c2bcb 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI > bool > > config SH_TIMER_CMT > - bool "Renesas CMT timer driver" if COMPILE_TEST > + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) Parens not needed and the spaces after/before them even less so. [...] MBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 9/9/2016 2:43 PM, bd-phuc@jinso.co.jp wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
>
> Modify CMT config to support 64bit
>
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
> ---
> drivers/clocksource/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 5677886..62c2bcb 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI
> bool
>
> config SH_TIMER_CMT
> - bool "Renesas CMT timer driver" if COMPILE_TEST
> + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST )
Parens not needed and the spaces after/before them even less so.
[...]
MBR, Sergei
On 9/9/2016 2:43 PM, bd-phuc at jinso.co.jp wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
>
> Modify CMT config to support 64bit
>
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
> ---
> drivers/clocksource/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 5677886..62c2bcb 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI
> bool
>
> config SH_TIMER_CMT
> - bool "Renesas CMT timer driver" if COMPILE_TEST
> + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST )
Parens not needed and the spaces after/before them even less so.
[...]
MBR, Sergei
Hi Phuc-san, On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote: > Add documentation for new separate CMT0 and CMT1 DT compatible strings > for R-Car Gen3. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt > index 1a05c1b..72fd526 100644 > --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt > +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt > @@ -52,6 +52,8 @@ Required Properties: > (CMT[01] on r8a73a4, r8a7790 and r8a7791) > This is a fallback for the renesas,cmt-48-r8a73a4, > renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. > + - "renesas,cmt-48-gen3" for third generation 48-bit CMT > + (CMT[01] on r8a7795 and r8a7796) I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do not allow to differentiate between CMT0 and CMT1, which have different feature sets. Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4" (https://lkml.org/lkml/2016/3/14/433). Magnus: What's the status of your series? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Phuc-san, On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote: > Add documentation for new separate CMT0 and CMT1 DT compatible strings > for R-Car Gen3. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt > index 1a05c1b..72fd526 100644 > --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt > +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt > @@ -52,6 +52,8 @@ Required Properties: > (CMT[01] on r8a73a4, r8a7790 and r8a7791) > This is a fallback for the renesas,cmt-48-r8a73a4, > renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. > + - "renesas,cmt-48-gen3" for third generation 48-bit CMT > + (CMT[01] on r8a7795 and r8a7796) I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do not allow to differentiate between CMT0 and CMT1, which have different feature sets. Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4" (https://lkml.org/lkml/2016/3/14/433). Magnus: What's the status of your series? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Phuc-san, On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote: > Add documentation for new separate CMT0 and CMT1 DT compatible strings > for R-Car Gen3. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt > index 1a05c1b..72fd526 100644 > --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt > +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt > @@ -52,6 +52,8 @@ Required Properties: > (CMT[01] on r8a73a4, r8a7790 and r8a7791) > This is a fallback for the renesas,cmt-48-r8a73a4, > renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. > + - "renesas,cmt-48-gen3" for third generation 48-bit CMT > + (CMT[01] on r8a7795 and r8a7796) I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do not allow to differentiate between CMT0 and CMT1, which have different feature sets. Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4" (https://lkml.org/lkml/2016/3/14/433). Magnus: What's the status of your series? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Phuc-san, On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote: > Add documentation for new separate CMT0 and CMT1 DT compatible strings > for R-Car Gen3. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt > index 1a05c1b..72fd526 100644 > --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt > +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt > @@ -52,6 +52,8 @@ Required Properties: > (CMT[01] on r8a73a4, r8a7790 and r8a7791) > This is a fallback for the renesas,cmt-48-r8a73a4, > renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. > + - "renesas,cmt-48-gen3" for third generation 48-bit CMT > + (CMT[01] on r8a7795 and r8a7796) I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do not allow to differentiate between CMT0 and CMT1, which have different feature sets. Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4" (https://lkml.org/lkml/2016/3/14/433). Magnus: What's the status of your series? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Bui Duc, Thank you for the patch. On Friday 09 Sep 2016 20:43:13 bd-phuc@jinso.co.jp wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > Modify CMT config to support 64bit > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > drivers/clocksource/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 5677886..62c2bcb 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI > bool > > config SH_TIMER_CMT > - bool "Renesas CMT timer driver" if COMPILE_TEST > + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) I think you should instead add select SH_TIMER_CMT to the config ARCH_RENESAS section in arch/arm64/Kconfig.platforms > depends on GENERIC_CLOCKEVENTS > depends on HAS_IOMEM > default SYS_SUPPORTS_SH_CMT -- Regards, Laurent Pinchart
Hi Bui Duc, Thank you for the patch. On Friday 09 Sep 2016 20:43:13 bd-phuc@jinso.co.jp wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > Modify CMT config to support 64bit > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > drivers/clocksource/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 5677886..62c2bcb 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI > bool > > config SH_TIMER_CMT > - bool "Renesas CMT timer driver" if COMPILE_TEST > + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) I think you should instead add select SH_TIMER_CMT to the config ARCH_RENESAS section in arch/arm64/Kconfig.platforms > depends on GENERIC_CLOCKEVENTS > depends on HAS_IOMEM > default SYS_SUPPORTS_SH_CMT -- Regards, Laurent Pinchart
Hi Bui Duc, Thank you for the patch. On Friday 09 Sep 2016 20:43:13 bd-phuc at jinso.co.jp wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > Modify CMT config to support 64bit > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > drivers/clocksource/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 5677886..62c2bcb 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI > bool > > config SH_TIMER_CMT > - bool "Renesas CMT timer driver" if COMPILE_TEST > + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) I think you should instead add select SH_TIMER_CMT to the config ARCH_RENESAS section in arch/arm64/Kconfig.platforms > depends on GENERIC_CLOCKEVENTS > depends on HAS_IOMEM > default SYS_SUPPORTS_SH_CMT -- Regards, Laurent Pinchart
Hi Bui Duc, Thank you for the patch. On Friday 09 Sep 2016 20:43:12 bd-phuc@jinso.co.jp wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c > index 103c493..1542aef 100644 > --- a/drivers/clocksource/sh_cmt.c > +++ b/drivers/clocksource/sh_cmt.c > @@ -69,6 +69,7 @@ enum sh_cmt_model { > SH_CMT_32BIT_FAST, > SH_CMT_48BIT, > SH_CMT_48BIT_GEN2, > + SH_CMT_48BIT_GEN3, > }; > > struct sh_cmt_info { > @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { > .read_count = sh_cmt_read32, > .write_count = sh_cmt_write32, > }, > + [SH_CMT_48BIT_GEN3] = { > + .model = SH_CMT_48BIT_GEN3, > + .width = 32, > + .overflow_bit = SH_CMT32_CMCSR_CMF, > + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), > + .read_control = sh_cmt_read32, > + .write_control = sh_cmt_write32, > + .read_count = sh_cmt_read32, > + .write_count = sh_cmt_write32, > + }, > }; > > #define CMCSR 0 /* channel register */ > @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel > *ch, unsigned int index, ch->cmt = cmt; > ch->index = index; > ch->hwidx = hwidx; > + ch->timer_bit = hwidx; > > /* > * Compute the address of the channel control register block. For the > @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel > *ch, unsigned int index, case SH_CMT_48BIT_GEN2: > ch->iostart = cmt->mapbase + ch->hwidx * 0x100; > ch->ioctrl = ch->iostart + 0x10; > + ch->timer_bit = 0; > + break; > + case SH_CMT_48BIT_GEN3: > + ch->iostart = cmt->mapbase + ch->hwidx * 0x100; > + ch->ioctrl = ch->iostart + 0x10; > + ch->timer_bit = 0; > break; > } > > @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel > *ch, unsigned int index, ch->match_value = ch->max_match_value; > raw_spin_lock_init(&ch->lock); > > - ch->timer_bit = cmt->info->model = SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; > - > ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), > clockevent, clocksource); > if (ret) { > @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[] > __maybe_unused = { > { .compatible = "renesas,cmt-32-fast", .data > &sh_cmt_info[SH_CMT_32BIT_FAST] }, > { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] > }, > { .compatible = "renesas,cmt-48-gen2", .data > &sh_cmt_info[SH_CMT_48BIT_GEN2] }, > + { .compatible = "renesas,cmt-48-gen3", .data > &sh_cmt_info[SH_CMT_48BIT_GEN3] }, Given that the Gen2 and Gen3 CMT seem identical based on the above code, how about just using SH_CMT_48BIT_GEN2 here ? You wouldn't need any of the above changes. > { } > }; > MODULE_DEVICE_TABLE(of, sh_cmt_of_table); -- Regards, Laurent Pinchart
Hi Bui Duc, Thank you for the patch. On Friday 09 Sep 2016 20:43:12 bd-phuc@jinso.co.jp wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c > index 103c493..1542aef 100644 > --- a/drivers/clocksource/sh_cmt.c > +++ b/drivers/clocksource/sh_cmt.c > @@ -69,6 +69,7 @@ enum sh_cmt_model { > SH_CMT_32BIT_FAST, > SH_CMT_48BIT, > SH_CMT_48BIT_GEN2, > + SH_CMT_48BIT_GEN3, > }; > > struct sh_cmt_info { > @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { > .read_count = sh_cmt_read32, > .write_count = sh_cmt_write32, > }, > + [SH_CMT_48BIT_GEN3] = { > + .model = SH_CMT_48BIT_GEN3, > + .width = 32, > + .overflow_bit = SH_CMT32_CMCSR_CMF, > + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), > + .read_control = sh_cmt_read32, > + .write_control = sh_cmt_write32, > + .read_count = sh_cmt_read32, > + .write_count = sh_cmt_write32, > + }, > }; > > #define CMCSR 0 /* channel register */ > @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel > *ch, unsigned int index, ch->cmt = cmt; > ch->index = index; > ch->hwidx = hwidx; > + ch->timer_bit = hwidx; > > /* > * Compute the address of the channel control register block. For the > @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel > *ch, unsigned int index, case SH_CMT_48BIT_GEN2: > ch->iostart = cmt->mapbase + ch->hwidx * 0x100; > ch->ioctrl = ch->iostart + 0x10; > + ch->timer_bit = 0; > + break; > + case SH_CMT_48BIT_GEN3: > + ch->iostart = cmt->mapbase + ch->hwidx * 0x100; > + ch->ioctrl = ch->iostart + 0x10; > + ch->timer_bit = 0; > break; > } > > @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel > *ch, unsigned int index, ch->match_value = ch->max_match_value; > raw_spin_lock_init(&ch->lock); > > - ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; > - > ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), > clockevent, clocksource); > if (ret) { > @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[] > __maybe_unused = { > { .compatible = "renesas,cmt-32-fast", .data = > &sh_cmt_info[SH_CMT_32BIT_FAST] }, > { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] > }, > { .compatible = "renesas,cmt-48-gen2", .data = > &sh_cmt_info[SH_CMT_48BIT_GEN2] }, > + { .compatible = "renesas,cmt-48-gen3", .data = > &sh_cmt_info[SH_CMT_48BIT_GEN3] }, Given that the Gen2 and Gen3 CMT seem identical based on the above code, how about just using SH_CMT_48BIT_GEN2 here ? You wouldn't need any of the above changes. > { } > }; > MODULE_DEVICE_TABLE(of, sh_cmt_of_table); -- Regards, Laurent Pinchart
Hi Bui Duc, Thank you for the patch. On Friday 09 Sep 2016 20:43:12 bd-phuc at jinso.co.jp wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> > --- > drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c > index 103c493..1542aef 100644 > --- a/drivers/clocksource/sh_cmt.c > +++ b/drivers/clocksource/sh_cmt.c > @@ -69,6 +69,7 @@ enum sh_cmt_model { > SH_CMT_32BIT_FAST, > SH_CMT_48BIT, > SH_CMT_48BIT_GEN2, > + SH_CMT_48BIT_GEN3, > }; > > struct sh_cmt_info { > @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { > .read_count = sh_cmt_read32, > .write_count = sh_cmt_write32, > }, > + [SH_CMT_48BIT_GEN3] = { > + .model = SH_CMT_48BIT_GEN3, > + .width = 32, > + .overflow_bit = SH_CMT32_CMCSR_CMF, > + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), > + .read_control = sh_cmt_read32, > + .write_control = sh_cmt_write32, > + .read_count = sh_cmt_read32, > + .write_count = sh_cmt_write32, > + }, > }; > > #define CMCSR 0 /* channel register */ > @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel > *ch, unsigned int index, ch->cmt = cmt; > ch->index = index; > ch->hwidx = hwidx; > + ch->timer_bit = hwidx; > > /* > * Compute the address of the channel control register block. For the > @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel > *ch, unsigned int index, case SH_CMT_48BIT_GEN2: > ch->iostart = cmt->mapbase + ch->hwidx * 0x100; > ch->ioctrl = ch->iostart + 0x10; > + ch->timer_bit = 0; > + break; > + case SH_CMT_48BIT_GEN3: > + ch->iostart = cmt->mapbase + ch->hwidx * 0x100; > + ch->ioctrl = ch->iostart + 0x10; > + ch->timer_bit = 0; > break; > } > > @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel > *ch, unsigned int index, ch->match_value = ch->max_match_value; > raw_spin_lock_init(&ch->lock); > > - ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; > - > ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), > clockevent, clocksource); > if (ret) { > @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[] > __maybe_unused = { > { .compatible = "renesas,cmt-32-fast", .data = > &sh_cmt_info[SH_CMT_32BIT_FAST] }, > { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] > }, > { .compatible = "renesas,cmt-48-gen2", .data = > &sh_cmt_info[SH_CMT_48BIT_GEN2] }, > + { .compatible = "renesas,cmt-48-gen3", .data = > &sh_cmt_info[SH_CMT_48BIT_GEN3] }, Given that the Gen2 and Gen3 CMT seem identical based on the above code, how about just using SH_CMT_48BIT_GEN2 here ? You wouldn't need any of the above changes. > { } > }; > MODULE_DEVICE_TABLE(of, sh_cmt_of_table); -- Regards, Laurent Pinchart
Hi Laurent
Thank you for your comments.
> I think you should instead add
>
> select SH_TIMER_CMT
>
> to the config ARCH_RENESAS section in arch/arm64/Kconfig.platforms
I will update in V2.
--
Regards,
Bui Duc Phuc
Hi Laurent
Thank you for your comments.
> I think you should instead add
>
> select SH_TIMER_CMT
>
> to the config ARCH_RENESAS section in arch/arm64/Kconfig.platforms
I will update in V2.
--
Regards,
Bui Duc Phuc
Hi Laurent
Thank you for your comments.
> I think you should instead add
>
> select SH_TIMER_CMT
>
> to the config ARCH_RENESAS section in arch/arm64/Kconfig.platforms
I will update in V2.
--
Regards,
Bui Duc Phuc
On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
>
> This patch adds CMT module clocks for r8a7795 SoC.
>
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
(will queue in clk-renesas-for-v4.9)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
>
> This patch adds CMT module clocks for r8a7795 SoC.
>
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
(will queue in clk-renesas-for-v4.9)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
>
> This patch adds CMT module clocks for r8a7795 SoC.
>
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
(will queue in clk-renesas-for-v4.9)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote:
> From: Bui Duc Phuc <bd-phuc@jinso.co.jp>
>
> This patch adds CMT module clocks for r8a7795 SoC.
>
> Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
(will queue in clk-renesas-for-v4.9)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > This patch adds CMT module clocks for r8a7796 SoC. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> (will queue in clk-renesas-for-v4.9) > --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c > @@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { > }; > > static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { > + DEF_MOD("cmt3", 300, R8A7796_CLK_R), > + DEF_MOD("cmt2", 301, R8A7796_CLK_R), > + DEF_MOD("cmt1", 302, R8A7796_CLK_R), > + DEF_MOD("cmt0", 303, R8A7796_CLK_R), BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > This patch adds CMT module clocks for r8a7796 SoC. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> (will queue in clk-renesas-for-v4.9) > --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c > @@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { > }; > > static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { > + DEF_MOD("cmt3", 300, R8A7796_CLK_R), > + DEF_MOD("cmt2", 301, R8A7796_CLK_R), > + DEF_MOD("cmt1", 302, R8A7796_CLK_R), > + DEF_MOD("cmt0", 303, R8A7796_CLK_R), BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > This patch adds CMT module clocks for r8a7796 SoC. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> (will queue in clk-renesas-for-v4.9) > --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c > @@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { > }; > > static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { > + DEF_MOD("cmt3", 300, R8A7796_CLK_R), > + DEF_MOD("cmt2", 301, R8A7796_CLK_R), > + DEF_MOD("cmt1", 302, R8A7796_CLK_R), > + DEF_MOD("cmt0", 303, R8A7796_CLK_R), BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Fri, Sep 9, 2016 at 1:43 PM, <bd-phuc@jinso.co.jp> wrote: > From: Bui Duc Phuc <bd-phuc@jinso.co.jp> > > This patch adds CMT module clocks for r8a7796 SoC. > > Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> (will queue in clk-renesas-for-v4.9) > --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c > @@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { > }; > > static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { > + DEF_MOD("cmt3", 300, R8A7796_CLK_R), > + DEF_MOD("cmt2", 301, R8A7796_CLK_R), > + DEF_MOD("cmt1", 302, R8A7796_CLK_R), > + DEF_MOD("cmt0", 303, R8A7796_CLK_R), BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Dear Geert
Thank you for your review.
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> (will queue in clk-renesas-for-v4.9)
>
--
Regards,
Bui Duc Phuc
Dear Geert Thank you for your review. > Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> > > (will queue in clk-renesas-for-v4.9) > -- Regards, Bui Duc Phuc -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Dear Geert
Thank you for your review.
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> (will queue in clk-renesas-for-v4.9)
>
--
Regards,
Bui Duc Phuc
Dear Geert
Thank you for your review.
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> (will queue in clk-renesas-for-v4.9)
>
--
Regards,
Bui Duc Phuc
Dear Geert Thank you for your review. > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > (will queue in clk-renesas-for-v4.9) Thank you for helping me. > BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch). > > -- Regards, Bui Duc Phuc
Dear Geert Thank you for your review. > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > (will queue in clk-renesas-for-v4.9) Thank you for helping me. > BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch). > > -- Regards, Bui Duc Phuc
Dear Geert Thank you for your review. > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > (will queue in clk-renesas-for-v4.9) Thank you for helping me. > BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch). > > -- Regards, Bui Duc Phuc
Dear Geert Thank you for your review. > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > (will queue in clk-renesas-for-v4.9) Thank you for helping me. > BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch). > > -- Regards, Bui Duc Phuc
Dear Geert,
> I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do
> not allow to differentiate between CMT0 and CMT1, which have different feature
> sets.
>
> Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4"
> (https://lkml.org/lkml/2016/3/14/433).
>
> Magnus: What's the status of your series?
Thank for your comments. I will update in V2.
I am still waiting for Magnus's comments, but from my point of
view,Magnus's patches seem
support 32 bit counter only, they are not suitable for 48bit counter.
According to hardware manual, there has to be registers ( CMCSRH,
CMCNTH,CMCORH) set for 48 bit counter,
but I do not see the registers ( CMCSRH, CMCNTH,CMCORH) in Magnus's patches.
--
Regards,
Bui Duc Phuc
Dear Geert,
> I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do
> not allow to differentiate between CMT0 and CMT1, which have different feature
> sets.
>
> Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4"
> (https://lkml.org/lkml/2016/3/14/433).
>
> Magnus: What's the status of your series?
Thank for your comments. I will update in V2.
I am still waiting for Magnus's comments, but from my point of
view,Magnus's patches seem
support 32 bit counter only, they are not suitable for 48bit counter.
According to hardware manual, there has to be registers ( CMCSRH,
CMCNTH,CMCORH) set for 48 bit counter,
but I do not see the registers ( CMCSRH, CMCNTH,CMCORH) in Magnus's patches.
--
Regards,
Bui Duc Phuc
Dear Geert,
> I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do
> not allow to differentiate between CMT0 and CMT1, which have different feature
> sets.
>
> Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4"
> (https://lkml.org/lkml/2016/3/14/433).
>
> Magnus: What's the status of your series?
Thank for your comments. I will update in V2.
I am still waiting for Magnus's comments, but from my point of
view,Magnus's patches seem
support 32 bit counter only, they are not suitable for 48bit counter.
According to hardware manual, there has to be registers ( CMCSRH,
CMCNTH,CMCORH) set for 48 bit counter,
but I do not see the registers ( CMCSRH, CMCNTH,CMCORH) in Magnus's patches.
--
Regards,
Bui Duc Phuc
Dear Geert,
> I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do
> not allow to differentiate between CMT0 and CMT1, which have different feature
> sets.
>
> Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4"
> (https://lkml.org/lkml/2016/3/14/433).
>
> Magnus: What's the status of your series?
Thank for your comments. I will update in V2.
I am still waiting for Magnus's comments, but from my point of
view,Magnus's patches seem
support 32 bit counter only, they are not suitable for 48bit counter.
According to hardware manual, there has to be registers ( CMCSRH,
CMCNTH,CMCORH) set for 48 bit counter,
but I do not see the registers ( CMCSRH, CMCNTH,CMCORH) in Magnus's patches.
--
Regards,
Bui Duc Phuc