From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sowjanya Komatineni Subject: Re: [RFC PATCH v3 16/18] gpu: host1x: mipi: Split tegra_mipi_calibrate and tegra_mipi_wait Date: Fri, 17 Jul 2020 08:41:58 -0700 Message-ID: References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> <1594786855-26506-17-git-send-email-skomatineni@nvidia.com> <20d63eca-4b2b-584e-a391-a4fb64a16b40@nvidia.com> <4690e682-8495-2327-87c7-c2f06a7a479d@nvidia.com> <66812127-38cf-2af3-51c0-50edbe446e73@nvidia.com> <9b4fbf9d-d651-aa35-c0a6-b8f16aeb0900@gmail.com> <550f1796-67ca-5856-223d-c68360243954@nvidia.com> <080b30c7-1dce-dd2f-dd96-40f6e25da4d6@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <080b30c7-1dce-dd2f-dd96-40f6e25da4d6-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Content-Language: en-US Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Dmitry Osipenko , thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, frankc-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org, sakari.ailus-X3B1VOXEql0@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, helen.koike-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org Cc: sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 7/17/20 8:01 AM, Dmitry Osipenko wrote: > 17.07.2020 07:46, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > ... >> Looks like sequence posted in TRM need to be updated clearly for proper >> MIPI CAL start and wait. >> >> Correct steps should be like below >> >> 1. Set up CSI registers for use case such as number of lanes, virtual >> channel, etc. >> 2. Initialize and power up CSI CIL interface >> 3. Program MIPI CAL bias pads, cal configs, cal control registers and >> enable calibration start >> 4. Power up camera through the I2C interface and start sensor streaming >> through the I2C >> >> Note: All sensors might not leave pads in LP-11 state as sensor may be >> power down when not in use. >> >> So start streaming prior to checking for calibration done status as >> LP-11 -> HS transition happens during sensor stream and calibration >> logic can apply results to pads and update done status, >> >> 5. Wait for done signal from calibration logic >> >> 6. perform frame capture thru VI >> 7. Frame done, CSI goes back to stop state, LP11 >> >> Will work internally to correct sequence in TRM ... > Will be nice to have an updated TRM, thank you! > > Also, what about the auto-calibration? Isn't it needed to be enabled for > CSI? STARTCAL does one time calibration and with AUTOCAL calibration will be=20 triggered periodically. For pads PULLUP/PULLDN/TERM impedance calibration, we only need one-time=20 calibration on pads power up. We always use one time pads calibration for CSI. > >> In mipi driver will update as below to have mipi clk enabled till >> calibration status check is done. >> >> Always tegra_mipi_wait() followes tegra_mipi_calibrate() in both DSI and >> CSI. So below sequence should work good. >> >> tegra_mipi_calibrate() >> >> - clk_enable mipi cal >> - program mipi cal registers (bias pads cfgs, mipi cal ctrl and trigger >> calibration start) >> >> tegra_mipi_wait() >> - read mipi cal status and wait for active and done bits >> - clk_disable mipi cal > > Maybe then it should be better to rename the functions like this: > > tegra_mipi_calibrate() -> tegra_mipi_start_calibration() > tegra_mipi_wait() -> tegra_mipi_finish_calibration(). > > and there also should be tegra_mipi_cancel_calibration(). > > > Example: > > tegra_mipi_start_calibration(); > > ret =3D v4l2_subdev_call(subdev, video, s_stream, on); > if (ret < 0) { > tegra_mipi_cancel_calibration(); > goto err; > } > > tegra_mipi_finish_calibration(); > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 491EAC433E3 for ; Fri, 17 Jul 2020 15:38:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1FB132076D for ; Fri, 17 Jul 2020 15:38:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="MmFR4hMI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727854AbgGQPii (ORCPT ); Fri, 17 Jul 2020 11:38:38 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:4423 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726293AbgGQPih (ORCPT ); Fri, 17 Jul 2020 11:38:37 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 17 Jul 2020 08:37:37 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 17 Jul 2020 08:38:37 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 17 Jul 2020 08:38:37 -0700 Received: from [10.2.163.115] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 17 Jul 2020 15:38:36 +0000 Subject: Re: [RFC PATCH v3 16/18] gpu: host1x: mipi: Split tegra_mipi_calibrate and tegra_mipi_wait To: Dmitry Osipenko , , , , , , , CC: , , , , , , References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> <1594786855-26506-17-git-send-email-skomatineni@nvidia.com> <20d63eca-4b2b-584e-a391-a4fb64a16b40@nvidia.com> <4690e682-8495-2327-87c7-c2f06a7a479d@nvidia.com> <66812127-38cf-2af3-51c0-50edbe446e73@nvidia.com> <9b4fbf9d-d651-aa35-c0a6-b8f16aeb0900@gmail.com> <550f1796-67ca-5856-223d-c68360243954@nvidia.com> <080b30c7-1dce-dd2f-dd96-40f6e25da4d6@gmail.com> From: Sowjanya Komatineni Message-ID: Date: Fri, 17 Jul 2020 08:41:58 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <080b30c7-1dce-dd2f-dd96-40f6e25da4d6@gmail.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595000257; bh=BwQ54mkMiNyfXprqWjplx8huez0ofYFZmAj/V7xmfOg=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=MmFR4hMIZLpNgjGiHyv/ZezFZqR2R973bwrM7NbK947LTpR87DZCHpQ4IAVIJzpye WkiP6wYzl9Z2M8OJTAeJdzO5oCwk7zqrNZN3lf1zqGGpO6kGBw2S69xdTV5W0FulN3 G4VUQpKP/NJgaVFeuV3hscuu+1h0IOz75tsMrgiuZwKNwXcY7eWBuovgj4oCyfYJLg /roJVJVnudOOpuC/ceTL/73FEIduJboJtIngXdd6Gmzfou57zcBRmggwbgiuNI3uXN 0HOd4HdPcCb8HKhNpjHl1xyeb+lCJrhIFKVmq9stGs7qSK3N19jxxHL+BgRZwrtDy1 EfoT6jLaO3WrA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/17/20 8:01 AM, Dmitry Osipenko wrote: > 17.07.2020 07:46, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > ... >> Looks like sequence posted in TRM need to be updated clearly for proper >> MIPI CAL start and wait. >> >> Correct steps should be like below >> >> 1. Set up CSI registers for use case such as number of lanes, virtual >> channel, etc. >> 2. Initialize and power up CSI CIL interface >> 3. Program MIPI CAL bias pads, cal configs, cal control registers and >> enable calibration start >> 4. Power up camera through the I2C interface and start sensor streaming >> through the I2C >> >> Note: All sensors might not leave pads in LP-11 state as sensor may be >> power down when not in use. >> >> So start streaming prior to checking for calibration done status as >> LP-11 -> HS transition happens during sensor stream and calibration >> logic can apply results to pads and update done status, >> >> 5. Wait for done signal from calibration logic >> >> 6. perform frame capture thru VI >> 7. Frame done, CSI goes back to stop state, LP11 >> >> Will work internally to correct sequence in TRM ... > Will be nice to have an updated TRM, thank you! > > Also, what about the auto-calibration? Isn't it needed to be enabled for > CSI? STARTCAL does one time calibration and with AUTOCAL calibration will be=20 triggered periodically. For pads PULLUP/PULLDN/TERM impedance calibration, we only need one-time=20 calibration on pads power up. We always use one time pads calibration for CSI. > >> In mipi driver will update as below to have mipi clk enabled till >> calibration status check is done. >> >> Always tegra_mipi_wait() followes tegra_mipi_calibrate() in both DSI and >> CSI. So below sequence should work good. >> >> tegra_mipi_calibrate() >> >> - clk_enable mipi cal >> - program mipi cal registers (bias pads cfgs, mipi cal ctrl and trigger >> calibration start) >> >> tegra_mipi_wait() >> - read mipi cal status and wait for active and done bits >> - clk_disable mipi cal > > Maybe then it should be better to rename the functions like this: > > tegra_mipi_calibrate() -> tegra_mipi_start_calibration() > tegra_mipi_wait() -> tegra_mipi_finish_calibration(). > > and there also should be tegra_mipi_cancel_calibration(). > > > Example: > > tegra_mipi_start_calibration(); > > ret =3D v4l2_subdev_call(subdev, video, s_stream, on); > if (ret < 0) { > tegra_mipi_cancel_calibration(); > goto err; > } > > tegra_mipi_finish_calibration(); > >