All of lore.kernel.org
 help / color / mirror / Atom feed
From: Patrice CHOTARD <patrice.chotard@foss.st.com>
To: Patrick Delaunay <patrick.delaunay@foss.st.com>, <u-boot@lists.denx.de>
Cc: Lionel Debieve <lionel.debieve@foss.st.com>,
	Heinrich Schuchardt <xypron.glpk@gmx.de>,
	Sughosh Ganu <sughosh.ganu@linaro.org>,
	<uboot-stm32@st-md-mailman.stormreply.com>
Subject: Re: [PATCH v2 02/10] rng: stm32mp1_rng: add conditional reset feature for STM32MP13x
Date: Thu, 7 Jul 2022 09:36:07 +0200	[thread overview]
Message-ID: <b1b353d9-e1b1-e54e-2a19-24055b719014@foss.st.com> (raw)
In-Reply-To: <20220630101930.v2.2.Idaf694f05913720a34cb73c69b896b6ce34a3d9a@changeid>

Hi Patrick

On 6/30/22 10:20, Patrick Delaunay wrote:
> From: Lionel Debieve <lionel.debieve@foss.st.com>
> 
> New IP adds a conditional reset that impact the clock
> error management. It is now linked to a new compatible.
> 
> Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
> ---
> 
> (no changes since v1)
> 
>  drivers/rng/stm32mp1_rng.c | 61 +++++++++++++++++++++++++++++---------
>  1 file changed, 47 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c
> index 8ea00e3e890..89da78c6c8b 100644
> --- a/drivers/rng/stm32mp1_rng.c
> +++ b/drivers/rng/stm32mp1_rng.c
> @@ -18,22 +18,28 @@
>  #include <linux/iopoll.h>
>  #include <linux/kernel.h>
>  
> -#define RNG_CR 0x00
> -#define RNG_CR_RNGEN BIT(2)
> -#define RNG_CR_CED BIT(5)
> +#define RNG_CR		0x00
> +#define RNG_CR_RNGEN	BIT(2)
> +#define RNG_CR_CED	BIT(5)
> +#define RNG_CR_CONDRST	BIT(30)
>  
> -#define RNG_SR 0x04
> -#define RNG_SR_SEIS BIT(6)
> -#define RNG_SR_CEIS BIT(5)
> -#define RNG_SR_SECS BIT(2)
> -#define RNG_SR_DRDY BIT(0)
> +#define RNG_SR		0x04
> +#define RNG_SR_SEIS	BIT(6)
> +#define RNG_SR_CEIS	BIT(5)
> +#define RNG_SR_SECS	BIT(2)
> +#define RNG_SR_DRDY	BIT(0)
>  
> -#define RNG_DR 0x08
> +#define RNG_DR		0x08
> +
> +struct stm32_rng_data {
> +	bool has_cond_reset;
> +};
>  
>  struct stm32_rng_plat {
>  	fdt_addr_t base;
>  	struct clk clk;
>  	struct reset_ctl rst;
> +	const struct stm32_rng_data *data;
>  };
>  
>  static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
> @@ -83,18 +89,36 @@ static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
>  static int stm32_rng_init(struct stm32_rng_plat *pdata)
>  {
>  	int err;
> +	u32 cr, sr;
>  
>  	err = clk_enable(&pdata->clk);
>  	if (err)
>  		return err;
>  
> +	cr = readl(pdata->base + RNG_CR);
> +
>  	/* Disable CED */
> -	writel(RNG_CR_RNGEN | RNG_CR_CED, pdata->base + RNG_CR);
> +	cr |= RNG_CR_CED;
> +	if (pdata->data->has_cond_reset) {
> +		cr |= RNG_CR_CONDRST;
> +		writel(cr, pdata->base + RNG_CR);
> +		cr &= ~RNG_CR_CONDRST;
> +		writel(cr, pdata->base + RNG_CR);
> +		err = readl_poll_timeout(pdata->base + RNG_CR, cr,
> +					 (!(cr & RNG_CR_CONDRST)), 10000);
> +		if (err)
> +			return err;
> +	}
>  
>  	/* clear error indicators */
>  	writel(0, pdata->base + RNG_SR);
>  
> -	return 0;
> +	cr |= RNG_CR_RNGEN;
> +	writel(cr, pdata->base + RNG_CR);
> +
> +	err = readl_poll_timeout(pdata->base + RNG_SR, sr,
> +				 sr & RNG_SR_DRDY, 10000);
> +	return err;
>  }
>  
>  static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
> @@ -108,6 +132,8 @@ static int stm32_rng_probe(struct udevice *dev)
>  {
>  	struct stm32_rng_plat *pdata = dev_get_plat(dev);
>  
> +	pdata->data = (struct stm32_rng_data *)dev_get_driver_data(dev);
> +
>  	reset_assert(&pdata->rst);
>  	udelay(20);
>  	reset_deassert(&pdata->rst);
> @@ -146,10 +172,17 @@ static const struct dm_rng_ops stm32_rng_ops = {
>  	.read = stm32_rng_read,
>  };
>  
> +static const struct stm32_rng_data stm32mp13_rng_data = {
> +	.has_cond_reset = true,
> +};
> +
> +static const struct stm32_rng_data stm32_rng_data = {
> +	.has_cond_reset = false,
> +};
> +
>  static const struct udevice_id stm32_rng_match[] = {
> -	{
> -		.compatible = "st,stm32-rng",
> -	},
> +	{.compatible = "st,stm32mp13-rng", .data = (ulong)&stm32mp13_rng_data},
> +	{.compatible = "st,stm32-rng", .data = (ulong)&stm32_rng_data},
>  	{},
>  };
>  
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks
Patrice

  reply	other threads:[~2022-07-07  7:36 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-30  8:20 [PATCH v2 01/10] i2c: stm32: add support for the st,stm32mp13 SOC Patrick Delaunay
2022-06-30  8:20 ` [PATCH v2 02/10] rng: stm32mp1_rng: add conditional reset feature for STM32MP13x Patrick Delaunay
2022-07-07  7:36   ` Patrice CHOTARD [this message]
2022-06-30  8:20 ` [PATCH v2 03/10] stm32mp: add support of STM32MP13x Rev.Y Patrick Delaunay
2022-07-07  7:38   ` Patrice CHOTARD
2022-06-30  8:20 ` [PATCH v2 04/10] ARM: dts: stm32mp13: alignment with v5.19 Patrick Delaunay
2022-07-07  7:38   ` Patrice CHOTARD
2022-06-30  8:20 ` [PATCH v2 05/10] ARM: dts: stm32mp13: activate led on STM32MP13F-DK Patrick Delaunay
2022-07-07  7:39   ` Patrice CHOTARD
2022-06-30  8:20 ` [PATCH v2 06/10] configs: stm32mp13: Add support for baudrates higher than 115200 Patrick Delaunay
2022-07-07  7:39   ` Patrice CHOTARD
2022-06-30  8:20 ` [PATCH v2 07/10] configs: stm32mp13: activate RNG support Patrick Delaunay
2022-07-07  7:40   ` Patrice CHOTARD
2022-06-30  8:20 ` [PATCH v2 08/10] configs: stm32mp13: activate RTC support Patrick Delaunay
2022-07-07  7:40   ` Patrice CHOTARD
2022-06-30  8:20 ` [PATCH v2 09/10] configs: stm32mp13: activate I2C support Patrick Delaunay
2022-07-07  7:40   ` Patrice CHOTARD
2022-06-30  8:20 ` [PATCH v2 10/10] configs: stm32mp13: activate some command Patrick Delaunay
2022-07-07  7:40   ` Patrice CHOTARD
2022-07-07  7:28 ` [PATCH v2 01/10] i2c: stm32: add support for the st, stm32mp13 SOC Patrice CHOTARD
2022-07-13 11:12 ` Patrick Delaunay

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=b1b353d9-e1b1-e54e-2a19-24055b719014@foss.st.com \
    --to=patrice.chotard@foss.st.com \
    --cc=lionel.debieve@foss.st.com \
    --cc=patrick.delaunay@foss.st.com \
    --cc=sughosh.ganu@linaro.org \
    --cc=u-boot@lists.denx.de \
    --cc=uboot-stm32@st-md-mailman.stormreply.com \
    --cc=xypron.glpk@gmx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.