From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Gonzalez Subject: Re: [PATCH v5] PCI: qcom: Use default config space read function Date: Fri, 29 Mar 2019 14:48:06 +0100 Message-ID: References: <94bb3f22-c5a7-1891-9d89-42a520e9a592@free.fr> <65321fe3-ca29-c454-63ae-98a46c2e5158@mm-sol.com> <1205cbfb-ac06-63a5-9401-75d4e68b15b5@free.fr> <38ad143b-3b07-4d19-8ccd-ca39fb51e53d@free.fr> <7d3d788a-d6a3-a70b-adab-6c65771cacc4@free.fr> <3c76613e-e60d-94b8-dd6f-b8f4e1928263@linaro.org> <2f901228-52db-7661-8257-ca8fd2ff2a46@free.fr> <29664b43-535c-c4b1-a93d-18f49687f929@linaro.org> <9c5a7620-e9ed-82d6-0708-34fe33e39030@linaro.org> <29d33e81-fe8d-7fd9-843d-cc53ea6c9586@free.fr> <8cd24928-54d0-c320-b53f-08332d434477@free.fr> <66ae38dc-1c0c-5a76-be23-fb87db90b327@free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <66ae38dc-1c0c-5a76-be23-fb87db90b327@free.fr> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Bjorn Andersson Cc: Stanimir Varbanov , Bjorn Helgaas , Srinivas Kandagatla , Andy Gross , David Brown , PCI , MSM , LKML , Jeffrey Hugo List-Id: linux-arm-msm@vger.kernel.org Bjorn, I think this patch is good enough to land now. Regards. On 25/03/2019 16:42, Marc Gonzalez wrote: > Move the device class fudge to a proper fixup function, and remove > qcom_pcie_rd_own_conf() which has become useless. > > NB: dw_pcie_setup_rc() already did the right thing, but it's broken > on older qcom chips, such as 8064. > > Signed-off-by: Marc Gonzalez > --- > Changes from v4 to v5: Apply fixup to all qcom chips, the same way it was before > (thus the code remains functionally equivalent) > Drop Srinivas' Tested-by tag because of the change > --- > drivers/pci/controller/dwc/pcie-qcom.c | 23 ++++++----------------- > 1 file changed, 6 insertions(+), 17 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index a7f703556790..0ed235d560e3 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1129,25 +1129,8 @@ static int qcom_pcie_host_init(struct pcie_port *pp) > return ret; > } > > -static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, > - u32 *val) > -{ > - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > - > - /* the device class is not reported correctly from the register */ > - if (where == PCI_CLASS_REVISION && size == 4) { > - *val = readl(pci->dbi_base + PCI_CLASS_REVISION); > - *val &= 0xff; /* keep revision id */ > - *val |= PCI_CLASS_BRIDGE_PCI << 16; > - return PCIBIOS_SUCCESSFUL; > - } > - > - return dw_pcie_read(pci->dbi_base + where, size, val); > -} > - > static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { > .host_init = qcom_pcie_host_init, > - .rd_own_conf = qcom_pcie_rd_own_conf, > }; > > /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ > @@ -1309,6 +1292,12 @@ static const struct of_device_id qcom_pcie_match[] = { > { } > }; > > +static void qcom_fixup_class(struct pci_dev *dev) > +{ > + dev->class = PCI_CLASS_BRIDGE_PCI << 8; > +} > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, PCI_ANY_ID, qcom_fixup_class); > + > static struct platform_driver qcom_pcie_driver = { > .probe = qcom_pcie_probe, > .driver = {