Hi Kevin,

On Mon, 20 May 2019 04:19:50 +0100,
kevin zhao <xiaoqiang.zhao@cloudminds.com> wrote:

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 Hi, there:

    I have seen some RFC about solving ARM64 kvm cache incoherency
issue ([1], [2]) in May 2015. I followed a few threads and did not
know how this arguments ends.

First, let me put things straight: there is no KVM/arm64 cache
coherency problem. The issue is that people expect behaviours that are
specific to x86 (such as coherency between cacheable and non-cacheable
aliases) to work on non-x86 architectures. This isn't a reasonable
expectation, unfortunately.

The patches you refer to try to workaround the issue by changing
either QEMU's or the kernel's behaviour. I contend that none of these
need to be changed, but instead the guest has to be fixed to properly
behave on the arm64 architecture, which includes things such as not
lying about what is a real device and what is an emulated one.

I've ranted publicly on this very subject a long while ago[1], with
all the gory details of what fails, why, and what the solutions
are. In the end, KVM/arm64 works remarkably well for what actually
matters, such as PV devices (virtio) and directly assigned devices,
without any cache coherency issue.

   Does anybody know how this problem  is solved finally ?

The architecture has gained the ARMv8.4 FWB extension, which solves
some of these problems by allowing Stage-2 to override the guest's
attributes (and a couple of other things that make I$/D$ coherency
much easier). Yes, it would have been nice to have this since day one
(circa 2008), but it involves getting hold of a crystal ball and a
time machine, both of which are out of stock at my local dealer.

I don't know of any publicly available CPU implementing FWB at this
stage, so this is a moot point...

Thanks,

	M.

[1] https://events.static.linuxfound.org/sites/events/files/slides/slides_10.pdf