From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from wout5-smtp.messagingengine.com (wout5-smtp.messagingengine.com [64.147.123.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B2FD136D for ; Fri, 12 Aug 2022 22:31:58 +0000 (UTC) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.west.internal (Postfix) with ESMTP id 01C0F32008FB; Fri, 12 Aug 2022 18:31:55 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute1.internal (MEProxy); Fri, 12 Aug 2022 18:31:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1660343515; x= 1660429915; bh=kgS42RQgG/tiE5VGji6aib4Oy9gURPck9Fi+x//w8eU=; b=y CsbGqpOkVSo0Xin2aC9GExcdGKs8UxUhKlgip+5w4IqZuVN8gWqzAP1JIB8gF2FJ oPg70bJH7vDXn+vjd012wOrsmGWOARsAvVBDtyX3V2cNFEt/7zApF9TtGAMsftTA L3rfxRfby+8Tk+M48jlZSbYMXmB90lMASMwpLl7CSIUswO4QYJhkCIvRvockDRc6 S2ybO3xop0kRYDvwJryn4QSrOXflD8/50GVWnxaCU1BD9UefYa8DiZtOgQ1r3NOS c1W4K8RDz9T1HlvB1aumy8MweCVVPitq6FVjJaFU5MayKGqrdmAYNLZIUTbccSOd vH5BN0Slo1ch9O5cY4TLw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1660343515; x= 1660429915; bh=kgS42RQgG/tiE5VGji6aib4Oy9gURPck9Fi+x//w8eU=; b=W j97d76GyyLi27VuagXD865UAWLlMXkhvJGZbd5+L6MdlFK6IZ3/3isSic4Y560kM h1KtXR3Q34AYqr6zhdudMoKZ0fi9zfOoSP4ExZqEYnVKtB9ti0W2AOkQl9YuA1Ct hNswG0cIbLt34mOBlrzF6SPuXDqHnOCUEnXsn0idHA3qGw947xNA2ewscuUsSSxL 0e67OLm8DdF6O1iID7Bsn5Mj1hk3vJoDrrHgUsWWJu+RziRejF0XGEWChO2gcFwA EQL9umR8VzQWGGtz/3Oq/E+mfHH/9XHHTNGX6eMm3j3otdJmSHVVOSHvn9l8kjAS Fl+h1wBWkzZkdK3g9bKNA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdegjedgudduucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepuffvvehfhffkffgfgggjtgfgsehtjeertddtfeejnecuhfhrohhmpefurghm uhgvlhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenuc ggtffrrghtthgvrhhnpefftdevkedvgeekueeutefgteffieelvedukeeuhfehledvhfei tdehudfhudehhfenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 12 Aug 2022 18:31:54 -0400 (EDT) Subject: Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last To: Paul Kocialkowski Cc: Kishon Vijay Abraham I , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard , Jagan Teki , Krzysztof Kozlowski , Maxime Ripard , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-sunxi@lists.linux.dev References: <20220812075603.59375-1-samuel@sholland.org> <20220812075603.59375-7-samuel@sholland.org> From: Samuel Holland Message-ID: Date: Fri, 12 Aug 2022 17:31:54 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Hi Paul, On 8/12/22 7:03 AM, Paul Kocialkowski wrote: > On Fri 12 Aug 22, 02:56, Samuel Holland wrote: >> The A100 variant of the DPHY requires configuring the analog registers >> before setting the global enable bit. Since this order also works on the >> other variants, always use it, to minimize the differences between them. > > Did you get a chance to actually test this with either DSI/CSI-2 hardware? I have tested DSI output with the Clockwork DevTerm (D1 SoC) and Pine64 PinePhone (A64 SoC). I do not have any MIPI CSI hardware to test with. > I vaguely remember that the order mattered. Do you have an idea of what the > Allwinner BSP does too? The Allwinner BSP makes the same change as this commit in its "lowlevel_v2x" copy of the code, which is used for R40 and T7 (original DPHY) and A100 and D1 (updated DPHY). It does not make the change in "lowlevel_sun50iw1" (A64 SoC, original DPHY), but I tested A64 with this change, and it works fine. > Otherwise I could give it a try, at least with my MIPI CSI-2 setup > that uses the driver. This commit only changes sun6i_dphy_tx_power_on(). The code for RX is unchanged -- in fact, it already sets SUN6I_DPHY_GCTL_REG last. Regards, Samuel >> Signed-off-by: Samuel Holland >> --- >> >> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c >> index 625c6e1e9990..9698d68d0db7 100644 >> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c >> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c >> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) >> SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) | >> SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3)); >> >> - regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, >> - SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | >> - SUN6I_DPHY_GCTL_EN); >> - >> regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, >> SUN6I_DPHY_ANA0_REG_PWS | >> SUN6I_DPHY_ANA0_REG_DMPC | >> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) >> SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK, >> SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask)); >> >> + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, >> + SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | >> + SUN6I_DPHY_GCTL_EN); >> + >> return 0; >> } >> >> -- >> 2.35.1 >> > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 755F7C00140 for ; Fri, 12 Aug 2022 22:33:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=e/PsKHIiWnYHYYyrxIapEcL0DrBPtfkvECM0DNMqKHg=; b=NUam1tpEp625knJkzPnMpFEyNv taAoJppYXVKSdBj4Oqj2oITqD2utAKDUzo1BjDSvPp2iCTU37mUoA7elLpOHicQwwLKPU8/s/s0Fr 0Mg1Qy6exMaTrCHEXnN47fH9Bw0CXjCnEnFGk2aLXtyAiacDxLUStr6Dy3RnkU2Z19uoU5T2Hh9Ei k2vWthA7ptaBckmYSxaePpjyoxgkR+TjPmqqtOjQ96VCGix5kK5I8j3+7pWOJraPUH+MknILt1/JH mTkw61dJQ8Id/1ncYKaEsiUCd6PGecAsL7eOp8Pv+36nbMTNvyBezKM4OgYF7qWKGNhpRlVAiEWbX h4Wbc3Nw==; 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Fri, 12 Aug 2022 18:31:54 -0400 (EDT) Subject: Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last To: Paul Kocialkowski Cc: Kishon Vijay Abraham I , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard , Jagan Teki , Krzysztof Kozlowski , Maxime Ripard , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-sunxi@lists.linux.dev References: <20220812075603.59375-1-samuel@sholland.org> <20220812075603.59375-7-samuel@sholland.org> From: Samuel Holland Message-ID: Date: Fri, 12 Aug 2022 17:31:54 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220812_153158_914761_73D71EA8 X-CRM114-Status: GOOD ( 21.73 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi Paul, On 8/12/22 7:03 AM, Paul Kocialkowski wrote: > On Fri 12 Aug 22, 02:56, Samuel Holland wrote: >> The A100 variant of the DPHY requires configuring the analog registers >> before setting the global enable bit. Since this order also works on the >> other variants, always use it, to minimize the differences between them. > > Did you get a chance to actually test this with either DSI/CSI-2 hardware? I have tested DSI output with the Clockwork DevTerm (D1 SoC) and Pine64 PinePhone (A64 SoC). I do not have any MIPI CSI hardware to test with. > I vaguely remember that the order mattered. Do you have an idea of what the > Allwinner BSP does too? The Allwinner BSP makes the same change as this commit in its "lowlevel_v2x" copy of the code, which is used for R40 and T7 (original DPHY) and A100 and D1 (updated DPHY). It does not make the change in "lowlevel_sun50iw1" (A64 SoC, original DPHY), but I tested A64 with this change, and it works fine. > Otherwise I could give it a try, at least with my MIPI CSI-2 setup > that uses the driver. This commit only changes sun6i_dphy_tx_power_on(). The code for RX is unchanged -- in fact, it already sets SUN6I_DPHY_GCTL_REG last. Regards, Samuel >> Signed-off-by: Samuel Holland >> --- >> >> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c >> index 625c6e1e9990..9698d68d0db7 100644 >> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c >> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c >> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) >> SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) | >> SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3)); >> >> - regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, >> - SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | >> - SUN6I_DPHY_GCTL_EN); >> - >> regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, >> SUN6I_DPHY_ANA0_REG_PWS | >> SUN6I_DPHY_ANA0_REG_DMPC | >> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) >> SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK, >> SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask)); >> >> + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, >> + SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | >> + SUN6I_DPHY_GCTL_EN); >> + >> return 0; >> } >> >> -- >> 2.35.1 >> > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 616D7C00140 for ; Fri, 12 Aug 2022 22:33:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; 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Fri, 12 Aug 2022 18:31:54 -0400 (EDT) Subject: Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last To: Paul Kocialkowski Cc: Kishon Vijay Abraham I , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard , Jagan Teki , Krzysztof Kozlowski , Maxime Ripard , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-sunxi@lists.linux.dev References: <20220812075603.59375-1-samuel@sholland.org> <20220812075603.59375-7-samuel@sholland.org> From: Samuel Holland Message-ID: Date: Fri, 12 Aug 2022 17:31:54 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220812_153158_914761_73D71EA8 X-CRM114-Status: GOOD ( 21.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Paul, On 8/12/22 7:03 AM, Paul Kocialkowski wrote: > On Fri 12 Aug 22, 02:56, Samuel Holland wrote: >> The A100 variant of the DPHY requires configuring the analog registers >> before setting the global enable bit. Since this order also works on the >> other variants, always use it, to minimize the differences between them. > > Did you get a chance to actually test this with either DSI/CSI-2 hardware? I have tested DSI output with the Clockwork DevTerm (D1 SoC) and Pine64 PinePhone (A64 SoC). I do not have any MIPI CSI hardware to test with. > I vaguely remember that the order mattered. Do you have an idea of what the > Allwinner BSP does too? The Allwinner BSP makes the same change as this commit in its "lowlevel_v2x" copy of the code, which is used for R40 and T7 (original DPHY) and A100 and D1 (updated DPHY). It does not make the change in "lowlevel_sun50iw1" (A64 SoC, original DPHY), but I tested A64 with this change, and it works fine. > Otherwise I could give it a try, at least with my MIPI CSI-2 setup > that uses the driver. This commit only changes sun6i_dphy_tx_power_on(). The code for RX is unchanged -- in fact, it already sets SUN6I_DPHY_GCTL_REG last. Regards, Samuel >> Signed-off-by: Samuel Holland >> --- >> >> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c >> index 625c6e1e9990..9698d68d0db7 100644 >> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c >> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c >> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) >> SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) | >> SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3)); >> >> - regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, >> - SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | >> - SUN6I_DPHY_GCTL_EN); >> - >> regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, >> SUN6I_DPHY_ANA0_REG_PWS | >> SUN6I_DPHY_ANA0_REG_DMPC | >> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) >> SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK, >> SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask)); >> >> + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, >> + SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | >> + SUN6I_DPHY_GCTL_EN); >> + >> return 0; >> } >> >> -- >> 2.35.1 >> > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel