From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47E98C433C1 for ; Tue, 30 Mar 2021 20:18:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C9CD617ED for ; Tue, 30 Mar 2021 20:18:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232201AbhC3URp (ORCPT ); Tue, 30 Mar 2021 16:17:45 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:27675 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232381AbhC3UR1 (ORCPT ); Tue, 30 Mar 2021 16:17:27 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1617135447; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: Cc: To: Subject: Sender; bh=aWJsC1i+UKFWbYGcd9fzYV+DRXIrKcOkq5eXKkiAk0M=; b=OG1wEnDgzFaRG+df3KP2QzNiUZx/yI1Fr8VT7fPTDiNZxhS/OjM79tcTonq2cpFMVQV7aYn0 fZVo5SQOu5iTVtm1RNjnNTmJGeO7SAY7tcogx/5nauNP0/gfN9UlnYGVnhLH1mShlbfeiY1j q7s3Im/xISOZ4lmHuLrIPMMV3Cc= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-west-2.postgun.com with SMTP id 60638743197975f05e04ea2b (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 30 Mar 2021 20:17:07 GMT Sender: wcheng=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9C4C7C433C6; Tue, 30 Mar 2021 20:17:06 +0000 (UTC) Received: from [10.110.60.140] (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: wcheng) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6DCACC433CA; Tue, 30 Mar 2021 20:17:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6DCACC433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=wcheng@codeaurora.org Subject: Re: [PATCH v3 2/2] usb: dwc3: Fix DRD mode change sequence following programming guide To: Thinh Nguyen , John Stultz , lkml Cc: Felipe Balbi , Tejas Joglekar , Yang Fei , YongQin Liu , Andrzej Pietrasiewicz , Jun Li , Mauro Carvalho Chehab , Greg Kroah-Hartman , "linux-usb@vger.kernel.org" References: <20210108015115.27920-1-john.stultz@linaro.org> <20210108015115.27920-2-john.stultz@linaro.org> <9af42bff-b083-18f0-1ea8-dca00af583af@synopsys.com> From: Wesley Cheng Message-ID: Date: Tue, 30 Mar 2021 13:17:03 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <9af42bff-b083-18f0-1ea8-dca00af583af@synopsys.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/29/2021 6:19 PM, Thinh Nguyen wrote: > Wesley Cheng wrote: >> >> >> On 3/6/2021 3:39 PM, Thinh Nguyen wrote: >>> Wesley Cheng wrote: >>>> >>>> On 1/7/2021 5:51 PM, John Stultz wrote: >>>>> In reviewing the previous patch, Thinh Nguyen pointed out that >>>>> the DRD mode change sequence should be like the following when >>>>> switching from host -> device according to the programming guide >>>>> (for all DRD IPs): >>>>> 1. Reset controller with GCTL.CoreSoftReset >>>>> 2. Set GCTL.PrtCapDir(device) >>>>> 3. Soft reset with DCTL.CSftRst >>>>> 4. Then follow up with the initializing registers sequence >>>>> >>>>> The current code does: >>>>> a. Soft reset with DCTL.CSftRst on driver probe >>>>> b. Reset controller with GCTL.CoreSoftReset (added in previous >>>>> patch) >>>>> c. Set GCTL.PrtCapDir(device) >>>>> d. < missing DCTL.CSftRst > >>>>> e. Then follow up with initializing registers sequence >>>>> >>>>> So this patch adds the DCTL.CSftRst soft reset that was currently >>>>> missing from the dwc3 mode switching. >>>>> >>>>> Cc: Felipe Balbi >>>>> Cc: Tejas Joglekar >>>>> Cc: Yang Fei >>>>> Cc: YongQin Liu >>>>> Cc: Andrzej Pietrasiewicz >>>>> Cc: Thinh Nguyen >>>>> Cc: Jun Li >>>>> Cc: Mauro Carvalho Chehab >>>>> Cc: Greg Kroah-Hartman >>>>> Cc: linux-usb@vger.kernel.org >>>>> Signed-off-by: John Stultz >>>>> --- >>>>> Feedback would be appreciated. I'm a little worried I should be >>>>> conditionalizing the DCTL.CSftRst on DRD mode controllers, but >>>>> I'm really not sure what the right thing to do is for non-DRD >>>>> mode controllers. >>>>> --- >>>>> drivers/usb/dwc3/core.c | 3 +++ >>>>> 1 file changed, 3 insertions(+) >>>>> >>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c >>>>> index b6a6b90eb2d5..71f8b07ecb99 100644 >>>>> --- a/drivers/usb/dwc3/core.c >>>>> +++ b/drivers/usb/dwc3/core.c >>>>> @@ -40,6 +40,8 @@ >>>>> >>>>> #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ >>>>> >>>>> +static int dwc3_core_soft_reset(struct dwc3 *dwc); >>>>> + >>>>> /** >>>>> * dwc3_get_dr_mode - Validates and sets dr_mode >>>>> * @dwc: pointer to our context structure >>>>> @@ -177,6 +179,7 @@ static void __dwc3_set_mode(struct work_struct *work) >>>>> >>>>> dwc3_set_prtcap(dwc, dwc->desired_dr_role); >>>>> >>>>> + dwc3_core_soft_reset(dwc); >>>> Hi John/Thinh/Felipe, >>>> >>>> I actually added this change into my local branch, because we were >>>> seeing an issue when switching from host mode --> peripheral mode. What >>>> was happening was that the RXFIFO register did not update back to the >>>> expected value for peripheral mode by the time >>>> dwc3_gadget_init_out_endpoint() was executed. With the logic to >>>> calculate the EP max packet limit based on RXFIFO reg, this caused all >>>> EPs to be set with an EP max limit of 0. >>>> >>>> With this change, it seemed to help with the above issue. However, can >>>> we consider moving the core soft reset outside the spinlock? At least >>>> with our PHY init routines, we have some msleep() calls for waiting for >>>> the PHYs to be ready, which will end up as a sleeping while atomic bug. >>>> (not sure if PHY init is required to be called in atomic context) >>>> >>>> Thanks >>>> Wesley Cheng >>> >>> Hi Wesley, >>> >>> Thanks for letting us know the issue you're having also. >>> >>> Yes, you need to wait a certain amount of time to synchronize with the >>> PHY (at least 50ms for dwc_usb32 and dwc_usb31 v1.80a and above, and >>> less for older versions). When removing the spinlock to use msleep(), >>> just make sure that there's no race issue. BTW, how long does your setup >>> need to msleep()? >>> >> Hi Thinh, >> >> Sorry for the late response. My mistake, its actually just a usleep() >> for a less than 100uS (polling for a status bit change, so it will exit >> early if possible). For this change, can we just move the >> dwc3_core_soft_reset() outside of the spinlock? >> >> Thanks >> Wesley Cheng >> > > > Hi Wesley, > > dwc3 can get notified at any time to queue a work to switch mode. So you > need protect it from a potential race. I think you can use a mutex for this. > Hi Thinh, OK let me take a look a bit more. > Also, what status are you polling? Note that there's no status bit for > GCTL.coresoftreset. For DCTL.CSFTRST, different controller versions > behave differently. Use dwc3_core_soft_reset() for DCTL.CSFTRST to get > the logic from there. > During dwc3_core_soft_reset() we're also calling the PHY init for both HS and SS PHYs. Within our PHY init sequence, we have a status bit check to make sure our PHY has initialized correctly. There was no issue using the usleep() yet, as dwc3_core_soft_reset() is also used during dwc3_core_init() w/o any locking. Thanks Wesley Cheng > 1 more thing, make sure that this flow only applies for DRD mode > controller and not OTG from older DWC_usb3 IP. > > Thanks, > Thinh > -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project