From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 603EFC433FE for ; Tue, 19 Apr 2022 17:30:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355755AbiDSRdb (ORCPT ); Tue, 19 Apr 2022 13:33:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344945AbiDSRdU (ORCPT ); Tue, 19 Apr 2022 13:33:20 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A69AE30F59; Tue, 19 Apr 2022 10:30:37 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23JHUHRe124234; Tue, 19 Apr 2022 12:30:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650389417; bh=tblmGe+8o+9ZJunF2//txAuP0QRnXYIGKc6iN9ViM60=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=x5Inx2bap9zeuEoC0XLd9dRiKWS+N1VbDsz8luum8ppgGOWnYcv5KbsJ5n1yljiI1 Kq0akeXJt8ncDnXS1xR+cuM0dEhDWKRvd9xIpFXHO+CH+Ge0hWCEJhhuOx94uBrFZ/ 5Ij9umpWFKke2Zw7tFkd2B2ia07HOnKGapZClKrY= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23JHUHM9019741 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Apr 2022 12:30:17 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Apr 2022 12:30:03 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Apr 2022 12:30:03 -0500 Received: from [10.0.3.15] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23JHTtBT041076; Tue, 19 Apr 2022 12:29:57 -0500 Message-ID: Date: Tue, 19 Apr 2022 22:59:54 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 0/2] Update register & interrupt info in am65x DSS Content-Language: en-US To: Tomi Valkeinen , Rob Herring , Nishanth Menon CC: Jyri Sarha , Vignesh Raghavendra , DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar References: <20220419070302.16502-1-a-bhatia1@ti.com> <9e848e84-a31f-98ec-ed6b-c1dce022723b@ideasonboard.com> From: Aradhya Bhatia In-Reply-To: <9e848e84-a31f-98ec-ed6b-c1dce022723b@ideasonboard.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/04/22 17:36, Tomi Valkeinen wrote: > On 19/04/2022 10:03, Aradhya Bhatia wrote: >> The Display SubSystem IP on the ti's am65x soc has an additional >> register space "common1" and services a maximum of 2 interrupts. >> >> The first patch in the series adds the required updates to the yaml >> file. The second patch then reflects the yaml updates in the DSS DT >> node of am65x soc. >> >> Aradhya Bhatia (2): >>    dt-bindings: display: ti,am65x-dss: Add missing register & interrupt >>    arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node >> >>   .../devicetree/bindings/display/ti/ti,am65x-dss.yaml   | 10 +++++++--- >>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi               |  6 ++++-- >>   2 files changed, 11 insertions(+), 5 deletions(-) >> > > Reviewed-by: Tomi Valkeinen > > How are you planning to use the common1 area? Tomi, Nishanth, Thank you for taking out time to review this. The DSS IP is such that it services 2 interrupts in case people want to use DSS from 2 SW entities (2nd VM or 2nd core). The regions "common" & "common1" cater registers for managing these 2 interrupts. Historically, on linux, only 1 interrupt and hence only the "common" region has been used. Therefore, the "common1" region is not actually required. The patches, thus, can be ignored. Rob, Thank you for pointing out the mistakes I have made. I will be more careful about them going further. > >  Tomi Regards Aradhya Bhatia From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FC4CC433EF for ; Tue, 19 Apr 2022 17:30:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 87D1010F137; Tue, 19 Apr 2022 17:30:35 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0562E10F134 for ; Tue, 19 Apr 2022 17:30:33 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23JHUHRe124234; Tue, 19 Apr 2022 12:30:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650389417; bh=tblmGe+8o+9ZJunF2//txAuP0QRnXYIGKc6iN9ViM60=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=x5Inx2bap9zeuEoC0XLd9dRiKWS+N1VbDsz8luum8ppgGOWnYcv5KbsJ5n1yljiI1 Kq0akeXJt8ncDnXS1xR+cuM0dEhDWKRvd9xIpFXHO+CH+Ge0hWCEJhhuOx94uBrFZ/ 5Ij9umpWFKke2Zw7tFkd2B2ia07HOnKGapZClKrY= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23JHUHM9019741 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Apr 2022 12:30:17 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Apr 2022 12:30:03 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Apr 2022 12:30:03 -0500 Received: from [10.0.3.15] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23JHTtBT041076; Tue, 19 Apr 2022 12:29:57 -0500 Message-ID: Date: Tue, 19 Apr 2022 22:59:54 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 0/2] Update register & interrupt info in am65x DSS Content-Language: en-US To: Tomi Valkeinen , Rob Herring , Nishanth Menon References: <20220419070302.16502-1-a-bhatia1@ti.com> <9e848e84-a31f-98ec-ed6b-c1dce022723b@ideasonboard.com> From: Aradhya Bhatia In-Reply-To: <9e848e84-a31f-98ec-ed6b-c1dce022723b@ideasonboard.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Devicetree , Vignesh Raghavendra , Linux Kernel , DRI Development , Jyri Sarha , Nikhil Devshatwar , Linux ARM Kernel Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 19/04/22 17:36, Tomi Valkeinen wrote: > On 19/04/2022 10:03, Aradhya Bhatia wrote: >> The Display SubSystem IP on the ti's am65x soc has an additional >> register space "common1" and services a maximum of 2 interrupts. >> >> The first patch in the series adds the required updates to the yaml >> file. The second patch then reflects the yaml updates in the DSS DT >> node of am65x soc. >> >> Aradhya Bhatia (2): >>    dt-bindings: display: ti,am65x-dss: Add missing register & interrupt >>    arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node >> >>   .../devicetree/bindings/display/ti/ti,am65x-dss.yaml   | 10 +++++++--- >>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi               |  6 ++++-- >>   2 files changed, 11 insertions(+), 5 deletions(-) >> > > Reviewed-by: Tomi Valkeinen > > How are you planning to use the common1 area? Tomi, Nishanth, Thank you for taking out time to review this. The DSS IP is such that it services 2 interrupts in case people want to use DSS from 2 SW entities (2nd VM or 2nd core). The regions "common" & "common1" cater registers for managing these 2 interrupts. Historically, on linux, only 1 interrupt and hence only the "common" region has been used. Therefore, the "common1" region is not actually required. The patches, thus, can be ignored. Rob, Thank you for pointing out the mistakes I have made. I will be more careful about them going further. > >  Tomi Regards Aradhya Bhatia From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 383DEC433F5 for ; Tue, 19 Apr 2022 17:43:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nLUCmx0TnqvNsmORrLxrXdbBJDmMIf1KO6cHNHQJi9Y=; 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charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CgpPbiAxOS8wNC8yMiAxNzozNiwgVG9taSBWYWxrZWluZW4gd3JvdGU6Cj4gT24gMTkvMDQvMjAy MiAxMDowMywgQXJhZGh5YSBCaGF0aWEgd3JvdGU6Cj4+IFRoZSBEaXNwbGF5IFN1YlN5c3RlbSBJ UCBvbiB0aGUgdGkncyBhbTY1eCBzb2MgaGFzIGFuIGFkZGl0aW9uYWwKPj4gcmVnaXN0ZXIgc3Bh Y2UgImNvbW1vbjEiIGFuZCBzZXJ2aWNlcyBhIG1heGltdW0gb2YgMiBpbnRlcnJ1cHRzLgo+Pgo+ PiBUaGUgZmlyc3QgcGF0Y2ggaW4gdGhlIHNlcmllcyBhZGRzIHRoZSByZXF1aXJlZCB1cGRhdGVz IHRvIHRoZSB5YW1sCj4+IGZpbGUuIFRoZSBzZWNvbmQgcGF0Y2ggdGhlbiByZWZsZWN0cyB0aGUg eWFtbCB1cGRhdGVzIGluIHRoZSBEU1MgRFQKPj4gbm9kZSBvZiBhbTY1eCBzb2MuCj4+Cj4+IEFy YWRoeWEgQmhhdGlhICgyKToKPj4gwqDCoCBkdC1iaW5kaW5nczogZGlzcGxheTogdGksYW02NXgt ZHNzOiBBZGQgbWlzc2luZyByZWdpc3RlciAmIGludGVycnVwdAo+PiDCoMKgIGFybTY0OiBkdHM6 IHRpOiBrMy1hbTY1OiBBZGQgbWlzc2luZyByZWdpc3RlciAmIGludGVycnVwdCBpbiBEU1Mgbm9k ZQo+Pgo+PiDCoCAuLi4vZGV2aWNldHJlZS9iaW5kaW5ncy9kaXNwbGF5L3RpL3RpLGFtNjV4LWRz cy55YW1swqDCoCB8IDEwICsrKysrKystLS0KPj4gwqAgYXJjaC9hcm02NC9ib290L2R0cy90aS9r My1hbTY1LW1haW4uZHRzacKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgfMKgIDYgKysrKy0t Cj4+IMKgIDIgZmlsZXMgY2hhbmdlZCwgMTEgaW5zZXJ0aW9ucygrKSwgNSBkZWxldGlvbnMoLSkK Pj4KPiAKPiBSZXZpZXdlZC1ieTogVG9taSBWYWxrZWluZW4gPHRvbWkudmFsa2VpbmVuQGlkZWFz b25ib2FyZC5jb20+Cj4gCj4gSG93IGFyZSB5b3UgcGxhbm5pbmcgdG8gdXNlIHRoZSBjb21tb24x IGFyZWE/ClRvbWksIE5pc2hhbnRoLApUaGFuayB5b3UgZm9yIHRha2luZyBvdXQgdGltZSB0byBy ZXZpZXcgdGhpcy4KClRoZSBEU1MgSVAgaXMgc3VjaCB0aGF0IGl0IHNlcnZpY2VzIDIgaW50ZXJy dXB0cyBpbiBjYXNlIHBlb3BsZSB3YW50IHRvCnVzZSBEU1MgZnJvbSAyIFNXIGVudGl0aWVzICgy bmQgVk0gb3IgMm5kIGNvcmUpLiBUaGUgcmVnaW9ucyAiY29tbW9uIiAmCiJjb21tb24xIiBjYXRl ciByZWdpc3RlcnMgZm9yIG1hbmFnaW5nIHRoZXNlIDIgaW50ZXJydXB0cy4KSGlzdG9yaWNhbGx5 LCBvbiBsaW51eCwgb25seSAxIGludGVycnVwdCBhbmQgaGVuY2Ugb25seSB0aGUgImNvbW1vbiIK cmVnaW9uIGhhcyBiZWVuIHVzZWQuIFRoZXJlZm9yZSwgdGhlICJjb21tb24xIiByZWdpb24gaXMg bm90IGFjdHVhbGx5CnJlcXVpcmVkLgoKVGhlIHBhdGNoZXMsIHRodXMsIGNhbiBiZSBpZ25vcmVk LgoKClJvYiwKVGhhbmsgeW91IGZvciBwb2ludGluZyBvdXQgdGhlIG1pc3Rha2VzIEkgaGF2ZSBt YWRlLiBJIHdpbGwgYmUgbW9yZQpjYXJlZnVsIGFib3V0IHRoZW0gZ29pbmcgZnVydGhlci4KCj4g Cj4gwqBUb21pCgpSZWdhcmRzCkFyYWRoeWEgQmhhdGlhCgpfX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdAps aW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVh ZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==