Am 23.12.2017 um 17:26 schrieb Alexander Kjeldaas:
>  Can the atomic ops work on the modified risers used for mining?

If the PCI bridge on the riser supports PCIe 3 atomic routing, then yes.

Regards,
  Felix

>
> On Dec 23, 2017 16:41, "Felix Kühling" <felix.kuehling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> <mailto:felix.kuehling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
>
>     As I understand it, it would require changes in the ROCr Runtime
>     and in
>     the firmware (MEC microcode). It also changes the programming
>     model, so
>     it may affect certain applications or higher level language runtimes
>     that rely on atomic operations.
>
>     Regards,
>       Felix
>
>
>     Am 19.12.2017 um 16:04 schrieb Tom Stellard:
>     > Hi,
>     >
>     > How hard of a requirement is PCIe3 atomics for dGPUs with the amdkfd
>     > kernel driver?  Is it possible to make modifications to the
>     runtime/kernel
>     > driver to drop this requirement?
>     >
>     > -Tom
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