From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78718C433F5 for ; Sat, 30 Apr 2022 19:26:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233453AbiD3T31 (ORCPT ); Sat, 30 Apr 2022 15:29:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244506AbiD3T30 (ORCPT ); Sat, 30 Apr 2022 15:29:26 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B21412458B for ; Sat, 30 Apr 2022 12:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651346763; x=1682882763; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=GE0avXmVVrsuQZrXU3xijktb7P/jhn4SI6UfdLFCW90=; b=la99bgQ21i8nUvoryz6vx4FsYK8hPcP3+cAxOTpK3SYyianw/e4p2wgw tQLVFFab1IbZwqtsxw0yr1Jbl7BuQ9uMglf6KfB+1l7vwlDJqTBhHRT1P yajmZu2IQI2gtpcLjyaHFqE3nirBQF6hFZDCH4juJY5SsEBjU4TuteJkE 0=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 30 Apr 2022 12:26:03 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2022 12:26:03 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 12:26:02 -0700 Received: from [10.38.245.205] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 12:26:00 -0700 Message-ID: Date: Sat, 30 Apr 2022 12:25:57 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing Content-Language: en-US To: Marijn Suijten , Dmitry Baryshkov CC: , kernel test robot , David Airlie , , , Stephen Boyd , "Rob Clark" , Daniel Vetter , Bjorn Andersson , Sean Paul References: <20220430175533.3817792-1-dmitry.baryshkov@linaro.org> <20220430185807.yn2j2coyc77qzx2o@SoMainline.org> From: Abhinav Kumar In-Reply-To: <20220430185807.yn2j2coyc77qzx2o@SoMainline.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 4/30/2022 11:58 AM, Marijn Suijten wrote: > On 2022-04-30 20:55:33, Dmitry Baryshkov wrote: >> The downstream uses read-modify-write for updating command mode >> compression registers. Let's follow this approach. This also fixes the >> following warning: >> >> drivers/gpu/drm/msm/dsi/dsi_host.c:918:23: warning: variable 'reg_ctrl' set but not used [-Wunused-but-set-variable] >> >> Reported-by: kernel test robot >> Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") >> Signed-off-by: Dmitry Baryshkov > > I pointed this out in review multiple times, so you'll obviously get my: > > Reviewed-by: Marijn Suijten > > (But are you sure there's nothing else to clear in the 1st CTRL > register, only the lowest 16 bits? That should mean `reg` never > contains anything in 0xffff0000) The top 16 bits contain information for stream 1. Stream 1 is unused. And whatever is the reset value we should retain that. So this patch is correct. > > However, this seems to indicate that the DSC patch series has been > approved and merged somehow?? > >> --- >> >> Changes since v1: >> - Fix c&p error and apply mask clear to reg_ctrl2 instead of reg_ctrl >> (Abhinav) >> >> --- >> drivers/gpu/drm/msm/dsi/dsi_host.c | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c >> index c983698d1384..a95d5df52653 100644 >> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c >> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c >> @@ -961,10 +961,13 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod >> reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); >> reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); >> >> + reg_ctrl &= ~0xffff; >> reg_ctrl |= reg; >> + >> + reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; >> reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(bytes_in_slice); >> >> - dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg); >> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); >> dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); >> } else { >> dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); >> -- >> 2.35.1 >> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6989CC433EF for ; Sat, 30 Apr 2022 19:26:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F0B7C10EA0E; Sat, 30 Apr 2022 19:26:05 +0000 (UTC) Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by gabe.freedesktop.org (Postfix) with ESMTPS id 492BC10EA0E; Sat, 30 Apr 2022 19:26:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651346764; x=1682882764; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=GE0avXmVVrsuQZrXU3xijktb7P/jhn4SI6UfdLFCW90=; b=f95Pjjbg+u8cTG5jHqunbJw+WWi9YRjxdTVUQfbXseMEkvqvt6icJ9y7 ysinOjfGM4IO6gIjR/pHmCONMK/LXBh1/oTzYrvwcWy3FZRqWQzBws1ka VQ3hAC9Vc2K2Za1r9c3s/6esoCO1K72YZXNQG9jN/CzNT5cIXyeKxrVQF U=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 30 Apr 2022 12:26:03 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2022 12:26:03 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 12:26:02 -0700 Received: from [10.38.245.205] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 12:26:00 -0700 Message-ID: Date: Sat, 30 Apr 2022 12:25:57 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing Content-Language: en-US To: Marijn Suijten , Dmitry Baryshkov References: <20220430175533.3817792-1-dmitry.baryshkov@linaro.org> <20220430185807.yn2j2coyc77qzx2o@SoMainline.org> From: Abhinav Kumar In-Reply-To: <20220430185807.yn2j2coyc77qzx2o@SoMainline.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sean Paul , kernel test robot , David Airlie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , Bjorn Andersson , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 4/30/2022 11:58 AM, Marijn Suijten wrote: > On 2022-04-30 20:55:33, Dmitry Baryshkov wrote: >> The downstream uses read-modify-write for updating command mode >> compression registers. Let's follow this approach. This also fixes the >> following warning: >> >> drivers/gpu/drm/msm/dsi/dsi_host.c:918:23: warning: variable 'reg_ctrl' set but not used [-Wunused-but-set-variable] >> >> Reported-by: kernel test robot >> Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") >> Signed-off-by: Dmitry Baryshkov > > I pointed this out in review multiple times, so you'll obviously get my: > > Reviewed-by: Marijn Suijten > > (But are you sure there's nothing else to clear in the 1st CTRL > register, only the lowest 16 bits? That should mean `reg` never > contains anything in 0xffff0000) The top 16 bits contain information for stream 1. Stream 1 is unused. And whatever is the reset value we should retain that. So this patch is correct. > > However, this seems to indicate that the DSC patch series has been > approved and merged somehow?? > >> --- >> >> Changes since v1: >> - Fix c&p error and apply mask clear to reg_ctrl2 instead of reg_ctrl >> (Abhinav) >> >> --- >> drivers/gpu/drm/msm/dsi/dsi_host.c | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c >> index c983698d1384..a95d5df52653 100644 >> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c >> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c >> @@ -961,10 +961,13 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod >> reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); >> reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); >> >> + reg_ctrl &= ~0xffff; >> reg_ctrl |= reg; >> + >> + reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; >> reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(bytes_in_slice); >> >> - dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg); >> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); >> dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); >> } else { >> dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); >> -- >> 2.35.1 >>