From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: Re: [RFC PATCH v4 8/8] arm64: tegra: Add Tegra VI CSI support in device tree Date: Sun, 15 Mar 2020 15:54:01 +0300 Message-ID: References: <1584236766-24819-1-git-send-email-skomatineni@nvidia.com> <1584236766-24819-9-git-send-email-skomatineni@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <1584236766-24819-9-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Content-Language: en-US Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Sowjanya Komatineni , thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, frankc-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org, helen.koike-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org, sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Cc: linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org 15.03.2020 04:46, Sowjanya Komatineni пишет: > Tegra210 contains VI controller for video input capture from MIPI > CSI camera sensors and also supports built-in test pattern generator. > > CSI ports can be one-to-one mapped to VI channels for capturing from > an external sensor or from built-in test pattern generator. > > This patch adds support for VI and CSI and enables them in Tegra210 > device tree. > > Signed-off-by: Sowjanya Komatineni > --- Hello Sowjanya, ... > + > + pd_venc: venc { > + clocks = <&tegra_car TEGRA210_CLK_VI>, > + <&tegra_car TEGRA210_CLK_CSI>; > + resets = <&tegra_car 20>, What is the clock #20? > + <&tegra_car TEGRA210_CLK_CSI>, > + <&mc TEGRA210_MC_RESET_VI>; Does this order means that memory controller will be reset *after* resetting the CSI/VI hardware? This is incorrect reset sequence. The memory controller reset should be kept asserted during of the time of the hardware resetting procedure. The correct sequence should be as follows: 1. Assert MC 2. Reset VI 3. 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[94.29.39.224]) by smtp.googlemail.com with ESMTPSA id v200sm4187853lfa.48.2020.03.15.05.54.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 15 Mar 2020 05:54:02 -0700 (PDT) Subject: Re: [RFC PATCH v4 8/8] arm64: tegra: Add Tegra VI CSI support in device tree To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, frankc@nvidia.com, hverkuil@xs4all.nl, helen.koike@collabora.com, sboyd@kernel.org Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <1584236766-24819-1-git-send-email-skomatineni@nvidia.com> <1584236766-24819-9-git-send-email-skomatineni@nvidia.com> From: Dmitry Osipenko Message-ID: Date: Sun, 15 Mar 2020 15:54:01 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <1584236766-24819-9-git-send-email-skomatineni@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 15.03.2020 04:46, Sowjanya Komatineni пишет: > Tegra210 contains VI controller for video input capture from MIPI > CSI camera sensors and also supports built-in test pattern generator. > > CSI ports can be one-to-one mapped to VI channels for capturing from > an external sensor or from built-in test pattern generator. > > This patch adds support for VI and CSI and enables them in Tegra210 > device tree. > > Signed-off-by: Sowjanya Komatineni > --- Hello Sowjanya, ... > + > + pd_venc: venc { > + clocks = <&tegra_car TEGRA210_CLK_VI>, > + <&tegra_car TEGRA210_CLK_CSI>; > + resets = <&tegra_car 20>, What is the clock #20? > + <&tegra_car TEGRA210_CLK_CSI>, > + <&mc TEGRA210_MC_RESET_VI>; Does this order means that memory controller will be reset *after* resetting the CSI/VI hardware? This is incorrect reset sequence. The memory controller reset should be kept asserted during of the time of the hardware resetting procedure. The correct sequence should be as follows: 1. Assert MC 2. Reset VI 3. Deassert MC