From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A998C2BA19 for ; Wed, 15 Apr 2020 10:39:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B28D206D9 for ; Wed, 15 Apr 2020 10:39:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408562AbgDOKji (ORCPT ); Wed, 15 Apr 2020 06:39:38 -0400 Received: from foss.arm.com ([217.140.110.172]:41946 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2408812AbgDOKit (ORCPT ); Wed, 15 Apr 2020 06:38:49 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E636A1063; Wed, 15 Apr 2020 03:38:48 -0700 (PDT) Received: from [10.37.12.1] (unknown [10.37.12.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C788E3F68F; Wed, 15 Apr 2020 03:38:46 -0700 (PDT) Subject: Re: [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only To: will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, catalin.marinas@arm.com, saiprakash.ranjan@codeaurora.org, dianders@chromium.org, kernel-team@android.com References: <20200414213114.2378-1-will@kernel.org> <20200414213114.2378-7-will@kernel.org> From: Suzuki K Poulose Message-ID: Date: Wed, 15 Apr 2020 11:43:36 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20200414213114.2378-7-will@kernel.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/14/2020 10:31 PM, Will Deacon wrote: > If AArch32 is not supported at EL1, the AArch32 feature register fields > no longer advertise support for some system features: > > * ISAR4.SMC > * PFR1.{Virt_frac, Sec_frac, Virtualization, Security, ProgMod} > > In which case, we don't need to emit "SANITY CHECK" failures for all of > them. > > Add logic to relax the strictness of individual feature register fields > at runtime and use this for the fields above if 32-bit EL1 is not > supported. > > Signed-off-by: Will Deacon Reviewed-by: Suzuki K Poulose From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A898C2BA19 for ; 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Wed, 15 Apr 2020 06:38:50 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tTn+kKVX1m9C for ; Wed, 15 Apr 2020 06:38:49 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 56BF04B113 for ; Wed, 15 Apr 2020 06:38:49 -0400 (EDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E636A1063; Wed, 15 Apr 2020 03:38:48 -0700 (PDT) Received: from [10.37.12.1] (unknown [10.37.12.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C788E3F68F; Wed, 15 Apr 2020 03:38:46 -0700 (PDT) Subject: Re: [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only To: will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu References: <20200414213114.2378-1-will@kernel.org> <20200414213114.2378-7-will@kernel.org> From: Suzuki K Poulose Message-ID: Date: Wed, 15 Apr 2020 11:43:36 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20200414213114.2378-7-will@kernel.org> Content-Language: en-US Cc: saiprakash.ranjan@codeaurora.org, anshuman.khandual@arm.com, maz@kernel.org, linux-kernel@vger.kernel.org, dianders@chromium.org, catalin.marinas@arm.com, kernel-team@android.com X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On 04/14/2020 10:31 PM, Will Deacon wrote: > If AArch32 is not supported at EL1, the AArch32 feature register fields > no longer advertise support for some system features: > > * ISAR4.SMC > * PFR1.{Virt_frac, Sec_frac, Virtualization, Security, ProgMod} > > In which case, we don't need to emit "SANITY CHECK" failures for all of > them. > > Add logic to relax the strictness of individual feature register fields > at runtime and use this for the fields above if 32-bit EL1 is not > supported. > > Signed-off-by: Will Deacon Reviewed-by: Suzuki K Poulose _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00676C2BB55 for ; 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Wed, 15 Apr 2020 03:38:46 -0700 (PDT) Subject: Re: [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only To: will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu References: <20200414213114.2378-1-will@kernel.org> <20200414213114.2378-7-will@kernel.org> From: Suzuki K Poulose Message-ID: Date: Wed, 15 Apr 2020 11:43:36 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20200414213114.2378-7-will@kernel.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200415_033849_749401_D35CBF35 X-CRM114-Status: GOOD ( 14.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, saiprakash.ranjan@codeaurora.org, anshuman.khandual@arm.com, maz@kernel.org, linux-kernel@vger.kernel.org, dianders@chromium.org, catalin.marinas@arm.com, kernel-team@android.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 04/14/2020 10:31 PM, Will Deacon wrote: > If AArch32 is not supported at EL1, the AArch32 feature register fields > no longer advertise support for some system features: > > * ISAR4.SMC > * PFR1.{Virt_frac, Sec_frac, Virtualization, Security, ProgMod} > > In which case, we don't need to emit "SANITY CHECK" failures for all of > them. > > Add logic to relax the strictness of individual feature register fields > at runtime and use this for the fields above if 32-bit EL1 is not > supported. > > Signed-off-by: Will Deacon Reviewed-by: Suzuki K Poulose _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel