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dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=prvs=285535d23a=patrice.chotard@foss.st.com Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 179CWUk9022594; Mon, 9 Aug 2021 14:33:01 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=70JJpea95VI85CWMm5coczHwexI2mOkaZfLfLE4UkY4=; b=z/soSn4OYJ/bxkHZXfNydOrF+AVo1hvHUN40evv0H0pUn0S/oB+9kZv1or9q/ORISaFO IUlOs0EBCDe1Dr/iE6vENVp10+Oq9MSfDIYNXCNKlrLzNEsZ23nnbvRoo9qujlaAqWVY tkMkJsLhBFbXEMPt/TnusD21Ju6Radc74+Bw1HbhSdjC4Kq4fM5tcNGNAWVOlr+FKfER vUFJ4Kw/To8u7KFO0+jQ8vSpRPitxHzYzmibgLpFnKOBgg2TKSVWQH+5HNZpDsFUBfxd ghCUHpEjc1cYx7O4rgZhsZb3CTtK5RMi/1MdN/zgMB1I/nYvuvHiorI0ySpEFde1McQ1 Ng== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 3aax1khyaa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 09 Aug 2021 14:33:01 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2FB9610002A; Mon, 9 Aug 2021 14:33:01 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1533422FA28; Mon, 9 Aug 2021 14:33:01 +0200 (CEST) Received: from lmecxl0573.lme.st.com (10.75.127.47) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 9 Aug 2021 14:33:00 +0200 Subject: Re: [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz To: Marek Vasut , CC: Patrick Delaunay References: <20210809120604.154080-1-marex@denx.de> From: Patrice CHOTARD Message-ID: Date: Mon, 9 Aug 2021 14:33:00 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210809120604.154080-1-marex@denx.de> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-09_04:2021-08-06, 2021-08-09 signatures=0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Marek On 8/9/21 2:06 PM, Marek Vasut wrote: > The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, > which causes additional signal delay. At 108 MHz, this delay triggers > a sporadic issue where the first bit of RX data is not received by the > QSPI controller. > > There are two options of addressing this problem, either by using the > DLYB block to compensate the extra delay, or by reducing the QSPI bus > clock frequency. The former requires calibration and that is overly > complex for SPL, so opt for the second option. This incurs 20ms delay > during boot, when SPL loads U-Boot to DRAM. > > Signed-off-by: Marek Vasut > Cc: Patrice Chotard > Cc: Patrick Delaunay > --- > arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi > index 64299df8166..94cf80dbede 100644 > --- a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi > +++ b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi > @@ -198,7 +198,7 @@ > compatible = "jedec,spi-nor"; > reg = <0>; > spi-rx-bus-width = <4>; > - spi-max-frequency = <108000000>; > + spi-max-frequency = <50000000>; > #address-cells = <1>; > #size-cells = <1>; > }; > Reviewed-by: Patrice Chotard Thanks Patrice