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Thu, 19 Aug 2021 09:57:40 -0700 (PDT) Received: from [192.168.3.43] ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id t15sm4785164pgi.80.2021.08.19.09.57.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Aug 2021 09:57:39 -0700 (PDT) Subject: Re: [PATCH 3/4] target/arm: Take an exception if PC is misaligned From: Richard Henderson To: Peter Maydell References: <20210818010041.337010-1-richard.henderson@linaro.org> <20210818010041.337010-4-richard.henderson@linaro.org> Message-ID: Date: Thu, 19 Aug 2021 06:57:36 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.591, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/19/21 6:50 AM, Richard Henderson wrote: > On 8/19/21 3:40 AM, Peter Maydell wrote: >>>       uint32_t insn; >>>       bool is_16bit; >>> >>> -    if (arm_pre_translate_insn(dc)) { >>> +    if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { >> >> >> Is it not possible to get a misaligned PC in the Thumb case ? > > No.  The thumb bit is always removed, leaving all pc aligned mod 2. > Both BXWritePC and BranchWritePC do this, as do we in gen_bx and store_reg. Do you think it's worth an assert here to make sure we never miss a case? I did an audit of the exception code and it looks like we mask everything correctly there, but... r~