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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id 65sm487965pfu.159.2021.06.02.15.19.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Jun 2021 15:19:22 -0700 (PDT) Subject: Re: [RFC PATCH] target/ppc: fix address translation bug for hash table mmus To: Bruno Piazera Larsen , qemu-devel@nongnu.org References: <20210602191822.90182-1-bruno.larsen@eldorado.org.br> <39c92ce9-46b8-4847-974c-647c7a5ca2ae@eldorado.org.br> From: Richard Henderson Message-ID: Date: Wed, 2 Jun 2021 15:19:20 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <39c92ce9-46b8-4847-974c-647c7a5ca2ae@eldorado.org.br> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.613, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/2/21 12:58 PM, Bruno Piazera Larsen wrote: >> For the use from ppc_cpu_get_phys_page_debug, you'd pass in >> cpu_mmu_index(env, false). > > ppc_cpu_get_phys_page_debug has 2 calls to ppc_xlate, one using the data MMU, > the other using the instruction MMU. I'm guessing I should pass both, right? Yes. > But here we have another bit that confuses me: cpu_mmu_index returns 0 if in > user mode, or uses the information stored in env to get it, so I don't see how > that would be different from getting directly. Unless the point is to have > ppc_*_xlate be generic and pc_*_debug knows the info in env is correct. Is that it? The issue is that (1) ppc_*_xlate should perform the lookup requested, and mmu_idx does not *necessarily* correspond to the current contents of env->msr et al. See (2). (2) There is a secondary call to ppc_radix64_partition_scoped_xlate for which the second stage page table should be read with hypervisor permissions, and not the permissions of the original memory access. Note that ppc_radix64_check_prot checks msr_pr directly. Thus the second stage lookup should use mmu_idx = 5 (HV kernel virtual mode). If I understand things correctly... > >> >> >>> +    const short HV = 1, IR = 2, DR = 3; >>> +    bool MSR[3]; >>> +    MSR[HV] = dmmu_idx & 2, >>> +    MSR[IR] = immu_idx & 4, >>> +    MSR[DR] = dmmu_idx & 4; >> >> There's no point in the array.  Just use three different scalars (real_mode, >> hv, and pr (note that pr is the major portion of the bug as reported)). >> Additionally, you'll not be distinguishing immu_idx and dmmu_idx, but using >> the single idx that's given. > > Ah, yeah, that's the "more complex than necessary, but it was easy for me to > read" part. Scalars are a good solution. In this function in specific, PR > doesn't actually show up anywhere, so I would actually only need 2. Anyway, > will start working on this. Oh, I'll note that your constants above are wrong. I think that you should have some common routines in (mmu-)internal.h: /* * These correspond to the mmu_idx values computed in * hreg_compute_hflags_value. See the tables therein. */ static inline bool mmuidx_pr(int idx) { return idx & 1; } static inline bool mmuidx_real(int idx) { return idx & 2; } static inline bool mmuidx_hv(int idx) { return idx & 4; } because you'll want to use these past mmu-radix64.c. Then you also have a single place to adjust if the mmu_idx are reordered at a later date. r~