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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id c2sm2211271wrp.46.2019.12.02.22.28.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 22:28:43 -0800 (PST) Subject: Re: [PATCH v4 37/40] target/arm: Move arm_excp_unmasked to cpu.c To: Richard Henderson , qemu-devel@nongnu.org References: <20191203022937.1474-1-richard.henderson@linaro.org> <20191203022937.1474-38-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 3 Dec 2019 07:28:42 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203022937.1474-38-richard.henderson@linaro.org> Content-Language: en-US X-MC-Unique: LK5rc4k5OsmTP6Vt-DgmhA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/3/19 3:29 AM, Richard Henderson wrote: > This inline function has one user in cpu.c, and need not be exposed > otherwise. Code movement only, with fixups for checkpatch. >=20 > Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=E9 > --- > target/arm/cpu.h | 111 ------------------------------------------- > target/arm/cpu.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 119 insertions(+), 111 deletions(-) >=20 > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 8e5aaaf415..22935e4433 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -2673,117 +2673,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm= _sync); > #define ARM_CPUID_TI915T 0x54029152 > #define ARM_CPUID_TI925T 0x54029252 > =20 > -static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx= , > - unsigned int target_el) > -{ > - CPUARMState *env =3D cs->env_ptr; > - unsigned int cur_el =3D arm_current_el(env); > - bool secure =3D arm_is_secure(env); > - bool pstate_unmasked; > - int8_t unmasked =3D 0; > - uint64_t hcr_el2; > - > - /* Don't take exceptions if they target a lower EL. > - * This check should catch any exceptions that would not be taken bu= t left > - * pending. > - */ > - if (cur_el > target_el) { > - return false; > - } > - > - hcr_el2 =3D arm_hcr_el2_eff(env); > - > - switch (excp_idx) { > - case EXCP_FIQ: > - pstate_unmasked =3D !(env->daif & PSTATE_F); > - break; > - > - case EXCP_IRQ: > - pstate_unmasked =3D !(env->daif & PSTATE_I); > - break; > - > - case EXCP_VFIQ: > - if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { > - /* VFIQs are only taken when hypervized and non-secure. */ > - return false; > - } > - return !(env->daif & PSTATE_F); > - case EXCP_VIRQ: > - if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { > - /* VIRQs are only taken when hypervized and non-secure. */ > - return false; > - } > - return !(env->daif & PSTATE_I); > - default: > - g_assert_not_reached(); > - } > - > - /* Use the target EL, current execution state and SCR/HCR settings t= o > - * determine whether the corresponding CPSR bit is used to mask the > - * interrupt. > - */ > - if ((target_el > cur_el) && (target_el !=3D 1)) { > - /* Exceptions targeting a higher EL may not be maskable */ > - if (arm_feature(env, ARM_FEATURE_AARCH64)) { > - /* 64-bit masking rules are simple: exceptions to EL3 > - * can't be masked, and exceptions to EL2 can only be > - * masked from Secure state. The HCR and SCR settings > - * don't affect the masking logic, only the interrupt routin= g. > - */ > - if (target_el =3D=3D 3 || !secure) { > - unmasked =3D 1; > - } > - } else { > - /* The old 32-bit-only environment has a more complicated > - * masking setup. HCR and SCR bits not only affect interrupt > - * routing but also change the behaviour of masking. > - */ > - bool hcr, scr; > - > - switch (excp_idx) { > - case EXCP_FIQ: > - /* If FIQs are routed to EL3 or EL2 then there are cases= where > - * we override the CPSR.F in determining if the exceptio= n is > - * masked or not. If neither of these are set then we fa= ll back > - * to the CPSR.F setting otherwise we further assess the= state > - * below. > - */ > - hcr =3D hcr_el2 & HCR_FMO; > - scr =3D (env->cp15.scr_el3 & SCR_FIQ); > - > - /* When EL3 is 32-bit, the SCR.FW bit controls whether t= he > - * CPSR.F bit masks FIQ interrupts when taken in non-sec= ure > - * state. If SCR.FW is set then FIQs can be masked by CP= SR.F > - * when non-secure but only when FIQs are only routed to= EL3. > - */ > - scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); > - break; > - case EXCP_IRQ: > - /* When EL3 execution state is 32-bit, if HCR.IMO is set= then > - * we may override the CPSR.I masking when in non-secure= state. > - * The SCR.IRQ setting has already been taken into consi= deration > - * when setting the target EL, so it does not have a fur= ther > - * affect here. > - */ > - hcr =3D hcr_el2 & HCR_IMO; > - scr =3D false; > - break; > - default: > - g_assert_not_reached(); > - } > - > - if ((scr || hcr) && !secure) { > - unmasked =3D 1; > - } > - } > - } > - > - /* The PSTATE bits only mask the interrupt if we have not overriden = the > - * ability above. > - */ > - return unmasked || pstate_unmasked; > -} > - > #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU > #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) > #define CPU_RESOLVING_TYPE TYPE_ARM_CPU > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 81c33221f7..a36344d4c7 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -410,6 +410,125 @@ static void arm_cpu_reset(CPUState *s) > arm_rebuild_hflags(env); > } > =20 > +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx= , > + unsigned int target_el) > +{ > + CPUARMState *env =3D cs->env_ptr; > + unsigned int cur_el =3D arm_current_el(env); > + bool secure =3D arm_is_secure(env); > + bool pstate_unmasked; > + int8_t unmasked =3D 0; > + uint64_t hcr_el2; > + > + /* > + * Don't take exceptions if they target a lower EL. > + * This check should catch any exceptions that would not be taken > + * but left pending. > + */ > + if (cur_el > target_el) { > + return false; > + } > + > + hcr_el2 =3D arm_hcr_el2_eff(env); > + > + switch (excp_idx) { > + case EXCP_FIQ: > + pstate_unmasked =3D !(env->daif & PSTATE_F); > + break; > + > + case EXCP_IRQ: > + pstate_unmasked =3D !(env->daif & PSTATE_I); > + break; > + > + case EXCP_VFIQ: > + if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { > + /* VFIQs are only taken when hypervized and non-secure. */ > + return false; > + } > + return !(env->daif & PSTATE_F); > + case EXCP_VIRQ: > + if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { > + /* VIRQs are only taken when hypervized and non-secure. */ > + return false; > + } > + return !(env->daif & PSTATE_I); > + default: > + g_assert_not_reached(); > + } > + > + /* > + * Use the target EL, current execution state and SCR/HCR settings t= o > + * determine whether the corresponding CPSR bit is used to mask the > + * interrupt. > + */ > + if ((target_el > cur_el) && (target_el !=3D 1)) { > + /* Exceptions targeting a higher EL may not be maskable */ > + if (arm_feature(env, ARM_FEATURE_AARCH64)) { > + /* > + * 64-bit masking rules are simple: exceptions to EL3 > + * can't be masked, and exceptions to EL2 can only be > + * masked from Secure state. The HCR and SCR settings > + * don't affect the masking logic, only the interrupt routin= g. > + */ > + if (target_el =3D=3D 3 || !secure) { > + unmasked =3D 1; > + } > + } else { > + /* > + * The old 32-bit-only environment has a more complicated > + * masking setup. HCR and SCR bits not only affect interrupt > + * routing but also change the behaviour of masking. > + */ > + bool hcr, scr; > + > + switch (excp_idx) { > + case EXCP_FIQ: > + /* > + * If FIQs are routed to EL3 or EL2 then there are cases= where > + * we override the CPSR.F in determining if the exceptio= n is > + * masked or not. If neither of these are set then we fa= ll back > + * to the CPSR.F setting otherwise we further assess the= state > + * below. > + */ > + hcr =3D hcr_el2 & HCR_FMO; > + scr =3D (env->cp15.scr_el3 & SCR_FIQ); > + > + /* > + * When EL3 is 32-bit, the SCR.FW bit controls whether t= he > + * CPSR.F bit masks FIQ interrupts when taken in non-sec= ure > + * state. If SCR.FW is set then FIQs can be masked by CP= SR.F > + * when non-secure but only when FIQs are only routed to= EL3. > + */ > + scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); > + break; > + case EXCP_IRQ: > + /* > + * When EL3 execution state is 32-bit, if HCR.IMO is set= then > + * we may override the CPSR.I masking when in non-secure= state. > + * The SCR.IRQ setting has already been taken into consi= deration > + * when setting the target EL, so it does not have a fur= ther > + * affect here. > + */ > + hcr =3D hcr_el2 & HCR_IMO; > + scr =3D false; > + break; > + default: > + g_assert_not_reached(); > + } > + > + if ((scr || hcr) && !secure) { > + unmasked =3D 1; > + } > + } > + } > + > + /* > + * The PSTATE bits only mask the interrupt if we have not overriden = the > + * ability above. > + */ > + return unmasked || pstate_unmasked; > +} > + > bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > { > CPUClass *cc =3D CPU_GET_CLASS(cs); >=20