From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: ACJfBosj2Ew1RGCNoGkUfrxGgjvJ6kVUI7vI71tfE/6h7hD1RvetTAhAXTh7xw/GHTVSNsrgHGMR ARC-Seal: i=1; a=rsa-sha256; t=1516211640; cv=none; d=google.com; s=arc-20160816; b=YI3HpRpXztRnlaoJ8/zm86J5hXp5mNDxVcFV7Str2w1BexenNOhFPhJGcQvAFE0sBx 5/fc6O43vjx9rEArmx1V2VfFepjQEtUBz5qzRD3WdgJAg0oRzegiGafVqP09cdfe4ZSP cYyaokezZKA7LZS+vZZaGokNeVbWTmFAa8k4WfKa/FQOJC4RnNxIOYnFhGj97p9RtxmS 8cu1YWONayGexAmJ+OJJSf9WyhM4/sju9GIDaDlue1yu1iDcXF8H6IIQUtijpahW435B goIMmJFSAfeP2HRNixJ5EW5o6rcAysMjoeHhujmSob6KRlHYJ4z9CbvRFS5DFcdHCg7u hvHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:content-language:in-reply-to:mime-version :user-agent:date:message-id:from:references:cc:to:subject :arc-authentication-results; bh=htcFJyAKOjGiBFPbj3UJfm//JV74PSPGd9X4sOk0+Zk=; b=Bvbyvfd26FcgFYKbNRPtVj2pwfDnxptN3GynIpM4VAWBq3rFcbm4boUm18M1OL9mRJ sYFeAXmn7iRGkW9N9P0OzVDGcQ+YyZFBhV9eonAUEknP58FIVWCbIB7oQL3cMENX85tO qrP+iO/b9QJrWiiPUF6b+KFWC0oyY83HgOY8fOoN/yrXSjALQrVHIWgFTFxZb0uAZQj8 TzFeR29nRXUw9k3vocZWvgcjrTFNg+kNUNkrNz7pz3cY2dupPDADst+EXAk7NM4fsxMQ p1WQzFqW2q7Do8Y2KOzX1P6gmhOUbrk04qCpMOpmM+SyBI4buwpMmlYiuscCvUOR6G29 Dgew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of pbonzini@redhat.com designates 209.132.183.28 as permitted sender) smtp.mailfrom=pbonzini@redhat.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of pbonzini@redhat.com designates 209.132.183.28 as permitted sender) smtp.mailfrom=pbonzini@redhat.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Subject: Re: [tip:x86/pti] x86/cpu/AMD: Use LFENCE_RDTSC instead of MFENCE_RDTSC To: Tom Lendacky , "Dr. David Alan Gilbert" , Andrew Cooper Cc: Thomas Gleixner , bp@alien8.de, dwmw@amazon.co.uk, gregkh@linux-foundation.org, pjt@google.com, mingo@kernel.org, linux-kernel@vger.kernel.org, hpa@zytor.com, tim.c.chen@linux.intel.com, torvalds@linux-foundation.org, peterz@infradead.org, Dave Hansen , Eduardo Habkost , "Sironi, Filippo" References: <20180105160756.23786.4220.stgit@tlendack-t1.amdoffice.net> <1b179b8b-6cc8-d736-81dc-2445be4baf02@citrix.com> <4d9a1f0d-a401-3f0f-9ee2-dd42f4b4716a@amd.com> <929a34a1-e3bc-b1c8-4c71-196610c0d02a@citrix.com> <20180108164803.GF2462@work-vm> <0be27b7e-7285-b23b-7eda-55a70338d16c@redhat.com> From: Paolo Bonzini Message-ID: Date: Wed, 17 Jan 2018 18:53:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1588769307376446817?= X-GMAIL-MSGID: =?utf-8?q?1589863136656373801?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On 17/01/2018 18:21, Tom Lendacky wrote: > On 1/8/2018 11:01 AM, Paolo Bonzini wrote: >> On 08/01/2018 17:48, Dr. David Alan Gilbert wrote: >>>> If your hypervisor is lying to you about the primary family, then all >>>> bets are off.  I don't expect there will be any production systems doing >>>> this. >>> It's not that an unusual thing to do on qemu/kvm - to specify the lowest >>> common denominator of the set of CPUs in your data centre (for any one >>> vendor); it does tend to get some weird combinations. >> >> Agreed. But on a hypervisor we pretty much know that: >> >> - the MSR_AMD64_DE_CFG doesn't exist unless you have a fix >> >> - setting the MSR_AMD64_DE_CFG bit to 1 if you have a fix can be done >> independent of the family >> >> So all KVM needs is a X86_FEATURE_LFENCE_SERIALIZE, it doesn't matter if >> it's because of the family or because Linux has set MSR_F10H_DE_CFG. >> The guest will either try setting the MSR bit and #GP, or it will find >> it already set and do nothing. >> >> Of course no code for this has been written yet. >> > > Hi Paolo, > > What would be the best way to approach the MSR support? I was thinking of > just recognizing a write to that MSR but not actually doing anything and, > on read, just returning a value with the single bit set if LFENCE is > serializing and not worrying about the full contents of the MSR. Or I > could save the value so that it could also be host initiated and only > allow the LFENCE serialization bit to be set if the LFENCE_RDTSC feature > is enabled. Yes, the latter is the correct one. We'll need changes in QEMU to add a new feature bit in "-cpu" too. The "-cpu" feature bit, if set, causes QEMU to set the bit in the MSR at CPU creation time. MSR-based features are not yet a thing in QEMU, but we were planning to add them before this whole kerfuffle started. But indeed we need to return also whether the feature is supported on the host, which would be similar to the first part (read-only, just returning a value with the single bit set is LFENCE is serializing). We would add KVM_GET_MSRS and KVM_GET_MSR_INDEX_LIST ioctls on the VM file descriptor for that, and a new capability KVM_CAP_GET_HOST_MSR (or KVM_CAP_GET_MSR_VM, you choose :)). QEMU can use these two ioctls to query the available MSR-based CPU features. These can include microcode version, VMX features, LFENCE serialization, IA32_ARCH_FACILITIES, etc. Thanks, Paolo