On 23/06/2018 15:54, speck for konrad.wilk_at_oracle.com wrote:
> +	if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
> +		wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
> +		return;
> +	}
> +
> +	/* FIXME: could this be boot_cpu_data.x86_cache_size * 2?  */
> +	size = PAGE_SIZE << L1D_CACHE_ORDER;

Regarding this "FIXME": Peter or Tim, do you know if loading 32KiB is
enough on pre-Skylake parts to clear the L1D cache?

Thanks,

Paolo