From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v3 5/6] drm/i915: Disable PSR2 while getting pipe CRC Date: Fri, 1 Mar 2019 22:18:44 +0000 Message-ID: References: <20190228013259.30026-1-jose.souza@intel.com> <20190228013259.30026-5-jose.souza@intel.com> <20190301204505.GT20097@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0852543840==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1508B6E337 for ; Fri, 1 Mar 2019 22:19:01 +0000 (UTC) In-Reply-To: <20190301204505.GT20097@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "ville.syrjala@linux.intel.com" Cc: "intel-gfx@lists.freedesktop.org" , "Pandiyan, Dhinakaran" List-Id: intel-gfx@lists.freedesktop.org --===============0852543840== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-bjT2KmwONKwTmLKfZKGq" --=-bjT2KmwONKwTmLKfZKGq Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2019-03-01 at 22:45 +0200, Ville Syrj=C3=A4l=C3=A4 wrote: > On Wed, Feb 27, 2019 at 05:32:58PM -0800, Jos=C3=A9 Roberto de Souza > wrote: > > When PSR2 is active aka after the number of frames programmed in > > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC > > interruptions causing IGT tests to fail due timeout. >=20 > I'm more concerned about the all ones (or was it all zeroes?) crc we > get when coming back from PSR. But I don't remmber right now if that > was limited PSR2 or if it happens with PSR1 as well. Have you looked > at that issue as well? Just wrote a test that gets 500 CRCs and the real difference between PSR1 and PSR2 is that PSR1 activation is blocked after the pipe CRC is enabled while on PSR2 that don't happen. After exit PSR2 I got more 4 CRC interruptions, 1 invalid value and 3 valid ones. Got the results above in a WHL and ICL. >=20 > > Oddly that don't happen when PSR1 active, so here it switches from > > PSR2 to PSR1 while user is requesting pipe CRC. > >=20 > > Force setting mode_changed as true is necessary to atomic checks > > functions compute new PSR state, that is why it was added to > > intel_crtc_crc_prepare(). > >=20 > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > >=20 > > v2: Changed commit description to describe that PSR2 inhibit CRC > > calculations. > >=20 > > Cc: Dhinakaran Pandiyan > > Cc: Ville Syrj=C3=A4l=C3=A4 > > Signed-off-by: Jos=C3=A9 Roberto de Souza > > --- > > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > > 2 files changed, 4 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c > > b/drivers/gpu/drm/i915/intel_pipe_crc.c > > index f6d0b2aaffe2..e7ac24c33650 100644 > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private > > *dev_priv, struct drm_crtc *crtc, > > goto put_state; > > } > > =20 > > + pipe_config->base.mode_changed =3D pipe_config->crc_enabled !=3D > > enable; > > pipe_config->crc_enabled =3D enable; > > =20 > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe =3D=3D PIPE_A) { > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 6175b1d2e0c8..f7730b8b2ec0 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > return false; > > } > > =20 > > + if (crtc_state->crc_enabled) > > + return false; > > + > > return true; > > } > > =20 > > --=20 > > 2.21.0 --=-bjT2KmwONKwTmLKfZKGq Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlx5r8IACgkQVenbO/mO WklGiQgAinkG2uNBjhomDpp1EbgimkjSHyBJAYbZvJDQJGDps81Nmu01BsLzsJkj 0pPztXGdkFceNhCTuJIbOhLF9h0W8BDrmnyJNAd368t52AzJa9Yq7phCD6yTLvtD WcyfM6rzHZbWwI1EGh/MsuljOCone5LKBxyj0n+IRVvbVawxs15reYEMyRDPAm5l X9+pR/rIj9PYAMnlqc3JzaOs3nLgg0n3KZu6PaWlfdPCtnFRMdU5gfdRkake+QkY BDVHXk07BVH0VsNFWUbqn3tj9wllmC/mNN2g4ZMk+nfj5qdpcraXtLwh3dfesrMx /Wnx7dggp7WB8AjNzXlSL54ho9EMaA== =rGb8 -----END PGP SIGNATURE----- --=-bjT2KmwONKwTmLKfZKGq-- --===============0852543840== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 --===============0852543840==--