From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:52693) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegF3-00056f-8I for qemu-devel@nongnu.org; Tue, 21 May 2013 02:40:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UegF1-0006Qh-W0 for qemu-devel@nongnu.org; Tue, 21 May 2013 02:40:13 -0400 Received: from mail-da0-x236.google.com ([2607:f8b0:400e:c00::236]:56001) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegF1-0006QT-J0 for qemu-devel@nongnu.org; Tue, 21 May 2013 02:40:11 -0400 Received: by mail-da0-f54.google.com with SMTP id z17so204751dal.27 for ; Mon, 20 May 2013 23:40:10 -0700 (PDT) Sender: Peter Crosthwaite From: peter.crosthwaite@xilinx.com Date: Tue, 21 May 2013 16:35:52 +1000 Message-Id: In-Reply-To: References: Subject: [Qemu-devel] [PATCH arm-devs v4 10/15] xilinx_spips: Fix CTRL register RW bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com From: Peter Crosthwaite The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- changed from v1 Macroified magic number (PMM review) hw/ssi/xilinx_spips.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ea8a593..3e9e76c 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -56,6 +56,7 @@ #define CLK_PH (1 << 2) #define CLK_POL (1 << 1) #define MODE_SEL (1 << 0) +#define R_CONFIG_RSVD (0x7bf40000) /* interrupt mechanism */ #define R_INTR_STATUS (0x04 / 4) @@ -355,7 +356,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); break; case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; @@ -415,7 +416,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); if (value & MAN_START_COM) { man_start_com = 1; } -- 1.8.3.rc1.44.gb387c77.dirty