Re: [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU

["Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>]

On Wednesday 22 February 2017 11:54 AM, Balbir Singh wrote:
> On Wed, Feb 22, 2017 at 10:42:02AM +0530, Aneesh Kumar K.V wrote:
>> We will set LPCR with correct value for radix during int. This make sure we
>> start with a sanitized value of LPCR. In case of kexec, cpus can have LPCR
>> value based on the previous translation mode we were running.
>>
>> Fixes: fe036a0605d60 ("powerpc/64/kexec: Fix MMU cleanup on radix")
>> Cc: stable@vger.kernel.org # v4.9+
>> Acked-by: Michael Neuling <mikey@neuling.org>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>>   arch/powerpc/kernel/cpu_setup_power.S | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
>> index 917188615bf5..7fe8c79e6937 100644
>> --- a/arch/powerpc/kernel/cpu_setup_power.S
>> +++ b/arch/powerpc/kernel/cpu_setup_power.S
>> @@ -101,6 +101,8 @@ _GLOBAL(__setup_cpu_power9)
>>   	mfspr	r3,SPRN_LPCR
>>   	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
>>   	or	r3, r3, r4
>> +	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
>> +	andc	r3, r3, r4
>>   	bl	__init_LPCR
>>   	bl	__init_HFSCR
>>   	bl	__init_tlb_power9
>> @@ -122,6 +124,8 @@ _GLOBAL(__restore_cpu_power9)
>>   	mfspr   r3,SPRN_LPCR
>>   	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
>>   	or	r3, r3, r4
>> +	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
>> +	andc	r3, r3, r4
>>   	bl	__init_LPCR
>>   	bl	__init_HFSCR
>>   	bl	__init_tlb_power9
> My previous comment mentions GTSE, but really we should be clearing
> LPCR to 0 and setting it to sane values in __init_LPCR
>
>
IIUC we do want to inherit values from firmware/skiboot. Hence the
explicit usage of mfspr/or. What we want to clear here are values we 
updated/changed
based on translation mode.

-aneesh