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Wed, 28 Apr 2021 15:18:35 +0000 Subject: Re: [PATCH 1/2] ASoC: dwc: add a quirk DW_I2S_QUIRK_STOP_ON_SHUTDOWN to dwc driver To: =?UTF-8?Q?P=c3=a9ter_Ujfalusi?= , Mark Brown Cc: alsa-devel@alsa-project.org, amistry@google.com, nartemiev@google.com, Alexander.Deucher@amd.com, Basavaraj.Hiregoudar@amd.com, Sunil-kumar.Dommati@amd.com, Jaroslav Kysela , Takashi Iwai , Liam Girdwood , Ranjani Sridharan , Kuninori Morimoto , open list References: <1619195089-29710-1-git-send-email-Vijendar.Mukunda@amd.com> <20210423164617.GG5507@sirena.org.uk> From: "Mukunda,Vijendar" Message-ID: Date: Wed, 28 Apr 2021 21:05:45 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [165.204.159.242] X-ClientProxiedBy: PN2PR01CA0043.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:22::18) To MWHPR1201MB2557.namprd12.prod.outlook.com (2603:10b6:300:e4::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [10.252.93.39] (165.204.159.242) by PN2PR01CA0043.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:22::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.27 via Frontend Transport; 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Driver is already upstreamed. Stoneyridge platform based products already into market and working fine with 4.14 kernel version. Currently Kernel migration from v4.14 to v5.10 is in progress for Stoneyridge platform and release got blocked due to Audio use cases failures. In v5.10 kernel base, re-ordering of stop trigger sequence is causing DMA channel stop failure for both playback & capture use cases. > > What is still not clear to me is which channel fails? > A) the DMA between ACP FIFO and the I2S > B) the DMA between ACP FIFO and system memory There is difference for playback and Capture use cases. Playback: channel 1 : DMA transfer from System memory -> ACP memory channel 2 : DMA transfer from ACP memory -> I2S memory Capture: channel 1: DMA transfer from I2S memory to ACP memory channel 2: DMA transfer from ACP memory to System memory In case of playback, Channel 2 is failing where as in case of capture channel 1 is failing. > > in acp-pcm-dma.c on stop you have a busy loop (10000 iterations) to > check if the channel is in fact stopped in response to the cleared run, > IOCEn bits and the set Rst bit. DMA channel run bit is cleared and Ioc bit also cleared for channel 2 in case of playback . After that as part of DMA stop sequence, DMA channel reset is applied. When DMA channel status is polled for stop, its failed to stop. > > Channel closer to the destination is stopped first which sounds > reasonable, but on playback you ignore timeout from A, on capture you > ignore the timeout from B. Please refer above explanation. > Still the issue sounds like exactly what I have described. One of the > DMA is failing to drain because the IP is stopped? As per our understanding, failing to stop the DMA by hardware is causing the issue. > >> Need find a right place to implement a work around only for AMD >> stoneyridge platform. > > Is this really only affecting stoneyridge platform? Are there other > platforms using drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c ? > This design is being used only in stoneyridge and Carrizo platforms. But only stoneyridge platform is productized. New design is implemented for later generations of APU series. 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Driver is already upstreamed. Stoneyridge platform based products already into market and working fine with 4.14 kernel version. Currently Kernel migration from v4.14 to v5.10 is in progress for Stoneyridge platform and release got blocked due to Audio use cases failures. In v5.10 kernel base, re-ordering of stop trigger sequence is causing DMA channel stop failure for both playback & capture use cases. > > What is still not clear to me is which channel fails? > A) the DMA between ACP FIFO and the I2S > B) the DMA between ACP FIFO and system memory There is difference for playback and Capture use cases. Playback: channel 1 : DMA transfer from System memory -> ACP memory channel 2 : DMA transfer from ACP memory -> I2S memory Capture: channel 1: DMA transfer from I2S memory to ACP memory channel 2: DMA transfer from ACP memory to System memory In case of playback, Channel 2 is failing where as in case of capture channel 1 is failing. > > in acp-pcm-dma.c on stop you have a busy loop (10000 iterations) to > check if the channel is in fact stopped in response to the cleared run, > IOCEn bits and the set Rst bit. DMA channel run bit is cleared and Ioc bit also cleared for channel 2 in case of playback . After that as part of DMA stop sequence, DMA channel reset is applied. When DMA channel status is polled for stop, its failed to stop. > > Channel closer to the destination is stopped first which sounds > reasonable, but on playback you ignore timeout from A, on capture you > ignore the timeout from B. Please refer above explanation. > Still the issue sounds like exactly what I have described. One of the > DMA is failing to drain because the IP is stopped? As per our understanding, failing to stop the DMA by hardware is causing the issue. > >> Need find a right place to implement a work around only for AMD >> stoneyridge platform. > > Is this really only affecting stoneyridge platform? Are there other > platforms using drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c ? > This design is being used only in stoneyridge and Carrizo platforms. But only stoneyridge platform is productized. New design is implemented for later generations of APU series.