From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-1.mimecast.com ([207.211.31.81]:42083 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726193AbgBRKCp (ORCPT ); Tue, 18 Feb 2020 05:02:45 -0500 Subject: Re: [PATCH v2 33/42] KVM: s390: protvirt: Mask PSW interrupt bits for interception 104 and 112 From: David Hildenbrand References: <20200214222658.12946-1-borntraeger@de.ibm.com> <20200214222658.12946-34-borntraeger@de.ibm.com> <70f30f71-f7f2-8286-aafb-ea5ca5fb86e9@redhat.com> Message-ID: Date: Tue, 18 Feb 2020 11:02:37 +0100 MIME-Version: 1.0 In-Reply-To: <70f30f71-f7f2-8286-aafb-ea5ca5fb86e9@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-s390-owner@vger.kernel.org List-ID: To: Christian Borntraeger , Janosch Frank Cc: KVM , Cornelia Huck , Thomas Huth , Ulrich Weigand , Claudio Imbrenda , linux-s390 , Michael Mueller , Vasily Gorbik , Janosch Frank On 18.02.20 10:53, David Hildenbrand wrote: > On 14.02.20 23:26, Christian Borntraeger wrote: >> From: Janosch Frank >> >> We're not allowed to inject interrupts on intercepts that leave the >> guest state in an "in-between" state where the next SIE entry will do a >> continuation, namely secure instruction interception (104) and secure >> prefix interception (112). >> As our PSW is just a copy of the real one that will be replaced on the >> next exit, we can mask out the interrupt bits in the PSW to make sure >> that we do not inject anything. >> >> Signed-off-by: Janosch Frank >> Reviewed-by: Thomas Huth >> Reviewed-by: Cornelia Huck >> [borntraeger@de.ibm.com: patch merging, splitting, fixing] >> Signed-off-by: Christian Borntraeger >> --- >> arch/s390/kvm/kvm-s390.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c >> index b6113285f47f..1b6963bbc96f 100644 >> --- a/arch/s390/kvm/kvm-s390.c >> +++ b/arch/s390/kvm/kvm-s390.c >> @@ -4025,6 +4025,7 @@ static int vcpu_post_run(struct kvm_vcpu *vcpu, int exit_reason) >> return vcpu_post_run_fault_in_sie(vcpu); >> } >> >> +#define PSW_INT_MASK (PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_MCHECK) >> static int __vcpu_run(struct kvm_vcpu *vcpu) >> { >> int rc, exit_reason; >> @@ -4061,6 +4062,16 @@ static int __vcpu_run(struct kvm_vcpu *vcpu) >> memcpy(vcpu->run->s.regs.gprs, >> sie_page->pv_grregs, >> sizeof(sie_page->pv_grregs)); >> + /* >> + * We're not allowed to inject interrupts on intercepts >> + * that leave the guest state in an "in-between" state >> + * where the next SIE entry will do a continuation. >> + * Fence interrupts in our "internal" PSW. >> + */ >> + if (vcpu->arch.sie_block->icptcode == ICPT_PV_INSTR || >> + vcpu->arch.sie_block->icptcode == ICPT_PV_PREF) { >> + vcpu->arch.sie_block->gpsw.mask &= ~PSW_INT_MASK; >> + } > > Is this actually the right approach? I mean, you lose PSW masks, but you > only want to teach the interrupt delivery code to skip delivering > interrupts until the intercept has been handled. Does not look clean to > me TBH. After reading the patch description again :) Reviewed-by: David Hildenbrand -- Thanks, David / dhildenb