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[176.184.7.144]) by smtp.gmail.com with ESMTPSA id g3-20020a5d4883000000b00336e32338f3sm19625625wrq.70.2024.01.03.05.21.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Jan 2024 05:21:54 -0800 (PST) Message-ID: Date: Wed, 3 Jan 2024 14:21:53 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/20] tcg/s390x: Implement vector NAND, NOR, EQV Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20211218194250.247633-1-richard.henderson@linaro.org> <20211218194250.247633-5-richard.henderson@linaro.org> Cc: =?UTF-8?Q?Alex_Benn=C3=A9e?= , qemu-s390x From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20211218194250.247633-5-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, (revisiting this old patch which is now commit 21eab5bfae) On 18/12/21 20:42, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/s390x/tcg-target.h | 6 +++--- > tcg/s390x/tcg-target.c.inc | 17 +++++++++++++++++ > 2 files changed, 20 insertions(+), 3 deletions(-) > > diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h > index ad29e62b16..fef227b0fe 100644 > --- a/tcg/s390x/tcg-target.h > +++ b/tcg/s390x/tcg-target.h > @@ -145,9 +145,9 @@ extern uint64_t s390_facilities[3]; > > #define TCG_TARGET_HAS_andc_vec 1 > #define TCG_TARGET_HAS_orc_vec HAVE_FACILITY(VECTOR_ENH1) > -#define TCG_TARGET_HAS_nand_vec 0 > -#define TCG_TARGET_HAS_nor_vec 0 > -#define TCG_TARGET_HAS_eqv_vec 0 > +#define TCG_TARGET_HAS_nand_vec HAVE_FACILITY(VECTOR_ENH1) > +#define TCG_TARGET_HAS_nor_vec 1 > +#define TCG_TARGET_HAS_eqv_vec HAVE_FACILITY(VECTOR_ENH1) Here some opcodes are conditional, ... > #define TCG_TARGET_HAS_not_vec 1 > #define TCG_TARGET_HAS_neg_vec 1 > #define TCG_TARGET_HAS_abs_vec 1 > diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc > index 57e803e339..5a90b892cb 100644 > --- a/tcg/s390x/tcg-target.c.inc > +++ b/tcg/s390x/tcg-target.c.inc > @@ -288,7 +288,9 @@ typedef enum S390Opcode { > VRRc_VMXL = 0xe7fd, > VRRc_VN = 0xe768, > VRRc_VNC = 0xe769, > + VRRc_VNN = 0xe76e, > VRRc_VNO = 0xe76b, > + VRRc_VNX = 0xe76c, > VRRc_VO = 0xe76a, > VRRc_VOC = 0xe76f, > VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ > @@ -2750,6 +2752,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, > case INDEX_op_xor_vec: > tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); > break; > + case INDEX_op_nand_vec: > + tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0); > + break; > + case INDEX_op_nor_vec: > + tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0); > + break; > + case INDEX_op_eqv_vec: > + tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0); > + break; > > case INDEX_op_shli_vec: > tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); > @@ -2846,7 +2857,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) > case INDEX_op_and_vec: > case INDEX_op_andc_vec: > case INDEX_op_bitsel_vec: > + case INDEX_op_eqv_vec: > + case INDEX_op_nand_vec: ... but here we unconditionally return 1 for them. Shouldn't we return TCG_TARGET_HAS_opcode instead? > case INDEX_op_neg_vec: > + case INDEX_op_nor_vec: > case INDEX_op_not_vec: > case INDEX_op_or_vec: > case INDEX_op_orc_vec: (expanding context) return 1; > @@ -3191,6 +3205,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) > case INDEX_op_or_vec: > case INDEX_op_orc_vec: > case INDEX_op_xor_vec: > + case INDEX_op_nand_vec: > + case INDEX_op_nor_vec: > + case INDEX_op_eqv_vec: > case INDEX_op_cmp_vec: > case INDEX_op_mul_vec: > case INDEX_op_rotlv_vec: