All of lore.kernel.org
 help / color / mirror / Atom feed
From: Laurent Vivier <laurent@vivier.eu>
To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PATCH v8 10/23] RISC-V Linux User Emulation
Date: Wed, 4 Apr 2018 14:44:47 +0200	[thread overview]
Message-ID: <b9b4f754-911c-8f23-8809-1a2d463f784e@vivier.eu> (raw)
In-Reply-To: <1519998711-73430-11-git-send-email-mjc@sifive.com>

Le 02/03/2018 à 14:51, Michael Clark a écrit :
> Implementation of linux user emulation for RISC-V.
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
>  linux-user/elfload.c              |  22 +++
>  linux-user/main.c                 |  99 +++++++++++++
>  linux-user/riscv/syscall_nr.h     | 287 ++++++++++++++++++++++++++++++++++++++
>  linux-user/riscv/target_cpu.h     |  18 +++
>  linux-user/riscv/target_elf.h     |  14 ++
>  linux-user/riscv/target_signal.h  |  23 +++
>  linux-user/riscv/target_structs.h |  46 ++++++
>  linux-user/riscv/target_syscall.h |  56 ++++++++
>  linux-user/riscv/termbits.h       | 222 +++++++++++++++++++++++++++++
>  linux-user/signal.c               | 203 ++++++++++++++++++++++++++-
>  linux-user/syscall.c              |   2 +
>  linux-user/syscall_defs.h         |  13 +-
>  target/riscv/cpu_user.h           |  13 ++
>  13 files changed, 1012 insertions(+), 6 deletions(-)
>  create mode 100644 linux-user/riscv/syscall_nr.h
>  create mode 100644 linux-user/riscv/target_cpu.h
>  create mode 100644 linux-user/riscv/target_elf.h
>  create mode 100644 linux-user/riscv/target_signal.h
>  create mode 100644 linux-user/riscv/target_structs.h
>  create mode 100644 linux-user/riscv/target_syscall.h
>  create mode 100644 linux-user/riscv/termbits.h
>  create mode 100644 target/riscv/cpu_user.h
> 
...
> diff --git a/linux-user/signal.c b/linux-user/signal.c
> index 9a380b9..4d3f244 100644
> --- a/linux-user/signal.c
> +++ b/linux-user/signal.c
...
> +static abi_ulong get_sigframe(struct target_sigaction *ka,
> +                              CPURISCVState *regs, size_t framesize)
> +{
> +    abi_ulong sp = regs->gpr[xSP];
> +    int onsigstack = on_sig_stack(sp);
> +
> +    /* redzone */
> +    /* This is the X/Open sanctioned signal stack switching.  */
> +    if ((ka->sa_flags & TARGET_SA_ONSTACK) != 0 && !onsigstack) {
> +        sp = target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_size;
> +    }
> +
> +    sp -= framesize;
> +    sp &= ~3UL; /* align sp on 4-byte boundary */

kernel aligns using 0xf. Why do you use a different alignment?

> +
> +    /* If we are on the alternate signal stack and would overflow it, don't.
> +       Return an always-bogus address instead so we will die with SIGSEGV. */
> +    if (onsigstack && !likely(on_sig_stack(sp))) {
> +        return -1L;
> +    }
> +
> +    return sp;
> +}
Other question why don't you use the same logic as in kernel?

1- check for signal stack overflow
2- check for X/Open sanctioned signal stack switching

static inline void __user *get_sigframe(struct ksignal *ksig,
        struct pt_regs *regs, size_t framesize)
{
        unsigned long sp;
        /* Default to using normal stack */
        sp = regs->sp;

        /*
         * If we are on the alternate signal stack and would overflow
it, don't.
         * Return an always-bogus address instead so we will die with
SIGSEGV.
         */
        if (on_sig_stack(sp) && !likely(on_sig_stack(sp - framesize)))
                return (void __user __force *)(-1UL);

        /* This is the X/Open sanctioned signal stack switching. */
        sp = sigsp(sp, ksig) - framesize;

        /* Align the stack frame. */
        sp &= ~0xfUL;

        return (void __user *)sp;
}

Thanks,
Laurent

  reply	other threads:[~2018-04-04 12:44 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-02 13:51 [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 01/23] RISC-V Maintainers Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 02/23] RISC-V ELF Machine Definition Michael Clark
2018-03-09 13:05   ` Philippe Mathieu-Daudé
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 03/23] RISC-V CPU Core Definition Michael Clark
2018-03-03  2:23   ` Michael Clark
2018-03-03  2:34     ` Michael Clark
2018-03-05  9:44   ` Igor Mammedov
2018-03-05 22:24     ` Michael Clark
2018-03-06  8:58       ` Igor Mammedov
2018-03-06 10:41         ` Igor Mammedov
2018-03-07  3:23         ` Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 04/23] RISC-V Disassembler Michael Clark
2018-04-27 12:26   ` Peter Maydell
2018-04-29 23:27     ` Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 05/23] RISC-V CPU Helpers Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 06/23] RISC-V FPU Support Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 07/23] RISC-V GDB Stub Michael Clark
2018-03-09 12:46   ` Philippe Mathieu-Daudé
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 08/23] RISC-V TCG Code Generation Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 09/23] RISC-V Physical Memory Protection Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 10/23] RISC-V Linux User Emulation Michael Clark
2018-04-04 12:44   ` Laurent Vivier [this message]
2018-04-08 20:59     ` Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 11/23] Add symbol table callback interface to load_elf Michael Clark
2018-03-09 11:34   ` Philippe Mathieu-Daudé
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 12/23] RISC-V HTIF Console Michael Clark
2018-03-09 11:52   ` Philippe Mathieu-Daudé
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 13/23] RISC-V HART Array Michael Clark
2018-03-09 12:52   ` Philippe Mathieu-Daudé
2018-03-09 13:48     ` Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 14/23] SiFive RISC-V CLINT Block Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 15/23] SiFive RISC-V PLIC Block Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 16/23] RISC-V Spike Machines Michael Clark
2018-03-09  4:50   ` Michael Clark
2018-05-14 16:49   ` Peter Maydell
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 17/23] SiFive RISC-V Test Finisher Michael Clark
2018-03-09 11:57   ` Philippe Mathieu-Daudé
2018-03-10  3:01     ` Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 18/23] RISC-V VirtIO Machine Michael Clark
2018-04-27 14:17   ` Peter Maydell
2018-04-30  0:18     ` Michael Clark
2018-04-30  7:49       ` Peter Maydell
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device Michael Clark
2018-03-09 12:39   ` Philippe Mathieu-Daudé
2018-03-10  3:02     ` Michael Clark
2018-03-10  9:40       ` Mark Cave-Ayland
2018-03-11 11:43         ` Bastian Koppelmann
2018-03-16 18:30           ` Michael Clark
2018-03-16 18:36             ` Michael Clark
2018-03-16 20:46               ` Bastian Koppelmann
2018-04-10  3:21   ` Antony Pavlov
2018-04-10  6:17     ` Thomas Huth
2018-04-10  8:04       ` Antony Pavlov
2018-04-11 21:12         ` Michael Clark
2018-04-11 22:25         ` Eric Blake
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 20/23] SiFive RISC-V PRCI Block Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 21/23] SiFive Freedom E Series RISC-V Machine Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 22/23] SiFive Freedom U " Michael Clark
2018-03-02 13:51 ` [Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure Michael Clark
2018-03-02 14:33   ` Eric Blake
2018-03-03  2:37     ` Michael Clark
2018-03-05 15:59       ` Eric Blake
2018-03-09 13:03   ` Philippe Mathieu-Daudé
2018-03-02 14:17 ` [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission no-reply
2018-03-05  8:41 ` Richard W.M. Jones
2018-03-05 10:02   ` Alex Bennée
2018-03-09 15:07   ` Michael Clark
2018-03-09 16:43   ` Peter Maydell
2018-03-09 18:27     ` Richard W.M. Jones

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=b9b4f754-911c-8f23-8809-1a2d463f784e@vivier.eu \
    --to=laurent@vivier.eu \
    --cc=kbastian@mail.uni-paderborn.de \
    --cc=mjc@sifive.com \
    --cc=palmer@sifive.com \
    --cc=patches@groups.riscv.org \
    --cc=qemu-devel@nongnu.org \
    --cc=sagark@eecs.berkeley.edu \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.