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From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: Frederic Barrat <fbarrat@linux.ibm.com>,
	clg@kaod.org, mst@redhat.com, marcel.apfelbaum@gmail.com,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 2/2] ppc/pnv: Remove LSI on the PCIE host bridge
Date: Fri, 8 Apr 2022 18:13:09 -0300	[thread overview]
Message-ID: <b9d7c268-c7bf-a383-5dfd-eba109ff8d38@gmail.com> (raw)
In-Reply-To: <20220408131303.147840-3-fbarrat@linux.ibm.com>



On 4/8/22 10:13, Frederic Barrat wrote:
> The phb3/phb4/phb5 root ports inherit from the default PCIE root port
> implementation, which requests a LSI interrupt (#INTA). On real
> hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch
> corrects it so that it matches the hardware.
> 
> As a consequence, the device tree previously generated was bogus, as
> the root bridge LSI was not properly mapped. On some
> implementation (powernv9), it was leading to inconsistent interrupt
> controller (xive) data. With this patch, it is now clean.
> 
> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
> ---

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>

>   hw/pci-host/pnv_phb3.c | 1 +
>   hw/pci-host/pnv_phb4.c | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
> index 6e9aa9d6ac..6a884833a8 100644
> --- a/hw/pci-host/pnv_phb3.c
> +++ b/hw/pci-host/pnv_phb3.c
> @@ -1162,6 +1162,7 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp)
>           error_propagate(errp, local_err);
>           return;
>       }
> +    pci_config_set_interrupt_pin(pci->config, 0);
>   }
>   
>   static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data)
> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
> index 11c97e27eb..dd81e940b7 100644
> --- a/hw/pci-host/pnv_phb4.c
> +++ b/hw/pci-host/pnv_phb4.c
> @@ -1772,6 +1772,7 @@ static void pnv_phb4_root_port_reset(DeviceState *dev)
>       pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
>       pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
>       pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
> +    pci_config_set_interrupt_pin(conf, 0);
>   }
>   
>   static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)


  reply	other threads:[~2022-04-08 21:14 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-08 13:13 [PATCH v2 0/2] Remove PCIE root bridge LSI on powernv Frederic Barrat
2022-04-08 13:13 ` [PATCH v2 1/2] pcie: Don't try triggering a LSI when not defined Frederic Barrat
2022-04-08 21:12   ` Daniel Henrique Barboza
2022-04-20 17:09   ` Daniel Henrique Barboza
2022-04-20 17:18   ` Michael S. Tsirkin
2022-04-08 13:13 ` [PATCH v2 2/2] ppc/pnv: Remove LSI on the PCIE host bridge Frederic Barrat
2022-04-08 21:13   ` Daniel Henrique Barboza [this message]
2022-04-20 19:17 ` [PATCH v2 0/2] Remove PCIE root bridge LSI on powernv Daniel Henrique Barboza

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