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From: Lijo Lazar <lijo.lazar@amd.com>
To: Darren Powell <darren.powell@amd.com>, amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/5] amdgpu/pm: simplify logic of smu_get_power_level
Date: Thu, 20 May 2021 14:02:33 +0530	[thread overview]
Message-ID: <b9dd5db1-78ba-4e0f-d107-43a75d5e1403@amd.com> (raw)
In-Reply-To: <20210520035722.4877-3-darren.powell@amd.com>



On 5/20/2021 9:27 AM, Darren Powell wrote:
>   new powerplay enumeration pp_power_limit_level
>   modify hwmon show_power functions to use pp_power_limit_level
>   remove insertion of byte field into smu_get_power_level output arg "limit"
>   modify smu_get_power_level to use pp_power_limit_level
>   simplify logic of smu_get_power_level
> 
> * Test
>   AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
>   AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
>   HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
> 
>   lspci -nn | grep "VGA\|Display" ; \
>   echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ;           \
>   echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ;   \
>   echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default
> 
> * Test (VANGOGH only)
>   echo "=== power2 cap ===" ; cat $HWMON_DIR/power2_cap ;           \
>   echo "=== power2 cap max ===" ; cat $HWMON_DIR/power2_cap_max ;   \
>   echo "=== power2 cap def ===" ; cat $HWMON_DIR/power2_cap_default
> 
> Signed-off-by: Darren Powell <darren.powell@amd.com>
> ---
>   .../gpu/drm/amd/include/kgd_pp_interface.h    | 11 +++++
>   drivers/gpu/drm/amd/pm/amdgpu_pm.c            | 18 ++++---
>   drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h       |  2 +-
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 47 ++++++++++++++-----
>   4 files changed, 59 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index e2d13131a432..cf98b9afb362 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -192,6 +192,17 @@ enum pp_df_cstate {
>   	DF_CSTATE_ALLOW,
>   };
>   
> +enum pp_power_limit_level
> +{
> +	PP_PWR_LIMIT_MIN = -1,
> +	PP_PWR_LIMIT_CURRENT,
> +	PP_PWR_LIMIT_DEFAULT,
> +	PP_PWR_LIMIT_MAX,
> +	PP_PWR_LIMIT_FAST_CURRENT,
> +	PP_PWR_LIMIT_FAST_DEFAULT,
> +	PP_PWR_LIMIT_FAST_MAX,
> +};
> +

Can't we keep the different limit types (DEFAULT/FAST/SLOW/SUSTAINED 
etc) and different levels(MIN/MAX/CURRENT) separate here also?

Thanks,
Lijo

>   #define PP_GROUP_MASK        0xF0000000
>   #define PP_GROUP_SHIFT       28
>   
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 13da377888d2..bd5af70ac739 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2718,7 +2718,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
>   	struct amdgpu_device *adev = dev_get_drvdata(dev);
>   	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
>   	int limit_type = to_sensor_dev_attr(attr)->index;
> -	uint32_t limit = limit_type << 24;
> +	uint32_t limit;
> +	enum pp_power_limit_level limit_level;
>   	uint32_t max_limit = 0;
>   	ssize_t size;
>   	int r;
> @@ -2734,8 +2735,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
>   		return r;
>   	}
>   
> +	limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_MAX : PP_PWR_LIMIT_MAX;
>   	if (is_support_sw_smu(adev)) {
> -		smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
> +		smu_get_power_limit(&adev->smu, &limit, limit_level);
>   		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
>   	} else if (pp_funcs && pp_funcs->get_power_limit) {
>   		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
> @@ -2758,7 +2760,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
>   	struct amdgpu_device *adev = dev_get_drvdata(dev);
>   	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
>   	int limit_type = to_sensor_dev_attr(attr)->index;
> -	uint32_t limit = limit_type << 24;
> +	uint32_t limit;
> +	enum pp_power_limit_level limit_level;
>   	ssize_t size;
>   	int r;
>   
> @@ -2773,8 +2776,9 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
>   		return r;
>   	}
>   
> +	limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_CURRENT : PP_PWR_LIMIT_CURRENT;
>   	if (is_support_sw_smu(adev)) {
> -		smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
> +		smu_get_power_limit(&adev->smu, &limit, limit_level);
>   		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
>   	} else if (pp_funcs && pp_funcs->get_power_limit) {
>   		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
> @@ -2797,7 +2801,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
>   	struct amdgpu_device *adev = dev_get_drvdata(dev);
>   	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
>   	int limit_type = to_sensor_dev_attr(attr)->index;
> -	uint32_t limit = limit_type << 24;
> +	uint32_t limit;
> +	enum pp_power_limit_level limit_level;
>   	ssize_t size;
>   	int r;
>   
> @@ -2812,8 +2817,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
>   		return r;
>   	}
>   
> +	limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_DEFAULT : PP_PWR_LIMIT_DEFAULT;
>   	if (is_support_sw_smu(adev)) {
> -		smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);
> +		smu_get_power_limit(&adev->smu, &limit, limit_level);
>   		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
>   	} else if (pp_funcs && pp_funcs->get_power_limit) {
>   		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 523f9d2982e9..6bdd112d64cb 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -1262,7 +1262,7 @@ enum smu_cmn2asic_mapping_type {
>   #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
>   int smu_get_power_limit(struct smu_context *smu,
>   			uint32_t *limit,
> -			enum smu_ppt_limit_level limit_level);
> +			enum pp_power_limit_level limit_level);
>   
>   bool smu_mode1_reset_is_support(struct smu_context *smu);
>   bool smu_mode2_reset_is_support(struct smu_context *smu);
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 8aff67a667fa..e192192e99d0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2168,33 +2168,56 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
>   
>   int smu_get_power_limit(struct smu_context *smu,
>   			uint32_t *limit,
> -			enum smu_ppt_limit_level limit_level)
> +			enum pp_power_limit_level pwr_limit_level)
>   {
> -	uint32_t limit_type = *limit >> 24;
> -	int ret = 0;
> +	enum smu_ppt_limit_level limit_level;
> +	enum smu_ppt_limit_type limit_type;
> +	int ret = -EOPNOTSUPP;
>   
>   	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
>   		return -EOPNOTSUPP;
>   
>   	mutex_lock(&smu->mutex);
>   
> -	if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
> -		if (smu->ppt_funcs->get_ppt_limit)
> -			ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
> -	} else {
> -		switch (limit_level) {
> -		case SMU_PPT_LIMIT_CURRENT:
> +	switch (pwr_limit_level) {
> +		case PP_PWR_LIMIT_CURRENT:
>   			*limit = smu->current_power_limit;
> +			ret = 0;
>   			break;
> -		case SMU_PPT_LIMIT_DEFAULT:
> +		case PP_PWR_LIMIT_DEFAULT:
>   			*limit = smu->default_power_limit;
> +			ret = 0;
>   			break;
> -		case SMU_PPT_LIMIT_MAX:
> +		case PP_PWR_LIMIT_MAX:
>   			*limit = smu->max_power_limit;
> +			ret = 0;
> +			break;
> +		case PP_PWR_LIMIT_FAST_CURRENT:
> +			if (smu->ppt_funcs->get_ppt_limit) {
> +				limit_type = SMU_FAST_PPT_LIMIT;
> +				limit_level = SMU_PPT_LIMIT_CURRENT;
> +				ret = smu->ppt_funcs->get_ppt_limit(smu,
> +					limit, limit_type, limit_level);
> +			}
> +			break;
> +		case PP_PWR_LIMIT_FAST_DEFAULT:
> +			if (smu->ppt_funcs->get_ppt_limit) {
> +				limit_type = SMU_FAST_PPT_LIMIT;
> +				limit_level = SMU_PPT_LIMIT_DEFAULT;
> +				ret = smu->ppt_funcs->get_ppt_limit(smu,
> +					limit, limit_type, limit_level);
> +			}
> +			break;
> +		case PP_PWR_LIMIT_FAST_MAX:
> +			if (smu->ppt_funcs->get_ppt_limit) {
> +				limit_type = SMU_FAST_PPT_LIMIT;
> +				limit_level = SMU_PPT_LIMIT_MAX;
> +				ret = smu->ppt_funcs->get_ppt_limit(smu,
> +					limit, limit_type, limit_level);
> +			}
>   			break;
>   		default:
>   			break;
> -		}
>   	}
>   
>   	mutex_unlock(&smu->mutex);
> 
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  reply	other threads:[~2021-05-20  8:33 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-20  3:57 [PATCH 0/5] Modify smu_get_power_limit to implement Powerplay API Darren Powell
2021-05-20  3:57 ` [PATCH 1/5] amdgpu/pm: reorder definition of swsmu_pm_funcs for readability Darren Powell
2021-05-20  3:57 ` [PATCH 2/5] amdgpu/pm: simplify logic of smu_get_power_level Darren Powell
2021-05-20  8:32   ` Lijo Lazar [this message]
2021-05-20  3:57 ` [PATCH 3/5] amdgpu/pm: modify Powerplay API get_power_limit to use pp_power_limit_level Darren Powell
2021-05-20  3:57 ` [PATCH 4/5] amdgpu/pm: modify smu_get_power_limit to implement Powerplay API Darren Powell
2021-05-20  3:57 ` [PATCH 5/5] amdgpu/pm: add kernel documentation for smu_get_power_limit Darren Powell

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