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[88.10.102.251]) by smtp.gmail.com with ESMTPSA id w125sm9216968wmg.32.2019.09.06.03.07.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Sep 2019 03:07:21 -0700 (PDT) To: Peter Maydell , Esteban Bosse , Andrew Baumann , qemu-devel@nongnu.org, Pekka Enberg , =?UTF-8?Q?Zolt=c3=a1n_Baldaszti?= References: <20190904171315.8354-1-f4bug@amsat.org> <20190904171315.8354-11-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: url=http://pgp.mit.edu/pks/lookup?op=get&search=0xE3E32C2CDEADC0DE Message-ID: Date: Fri, 6 Sep 2019 12:07:18 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190904171315.8354-11-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: Re: [Qemu-devel] [PATCH 10/14] hw/arm/raspi: Define various blocks base addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, Clement Deschamps , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Luc Michel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/4/19 7:13 PM, Philippe Mathieu-Daudé wrote: > The Raspberry firmware is closed-source. While running it, it > accesses various I/O registers. Logging these accesses as UNIMP > (unimplemented) help to understand what the firmware is doing > (ideally we want it able to boot a Linux kernel). > > Document various blocks we might use later. > > Adresses and names based on: > https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/hw/arm/raspi_platform.h | 49 +++++++++++++++++++++++++++------ > 1 file changed, 40 insertions(+), 9 deletions(-) > > diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h > index 069edab526..c6f4985522 100644 > --- a/include/hw/arm/raspi_platform.h > +++ b/include/hw/arm/raspi_platform.h > @@ -25,42 +25,73 @@ > #ifndef HW_ARM_RASPI_PLATFORM_H > #define HW_ARM_RASPI_PLATFORM_H > > -#define MCORE_OFFSET 0x0000 /* Fake frame buffer device > - * (the multicore sync block) */ > -#define IC0_OFFSET 0x2000 > +#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ > +#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */ > +#define INTE_OFFSET 0x2000 /* VC Interrupt controller */ > #define ST_OFFSET 0x3000 /* System Timer */ > +#define TXP_OFFSET 0x4000 > +#define JPEG_OFFSET 0x5000 > #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ > #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ > -#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */ > +#define ARBA_OFFSET 0x9000 > +#define BRDG_OFFSET 0xa000 > +#define ARM_OFFSET 0xB000 /* ARM control block */ > #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) > #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ > -#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ > +#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */ > #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores > * Doorbells & Mailboxes */ > #define PM_OFFSET 0x100000 /* Power Management, Reset controller > * and Watchdog registers */ > #define CPRMAN_OFFSET 0x101000 /* Clock Management */ > +#define A2W_OFFSET 0x102000 > #define AVS_OFFSET 0x103000 /* Audio Video Standard */ > #define RNG_OFFSET 0x104000 > #define GPIO_OFFSET 0x200000 > -#define UART0_OFFSET 0x201000 > -#define MMCI0_OFFSET 0x202000 > -#define I2S_OFFSET 0x203000 > -#define SPI0_OFFSET 0x204000 > +#define UART0_OFFSET 0x201000 /* PL011 */ > +#define MMCI0_OFFSET 0x202000 /* Legacy MMC */ > +#define I2S_OFFSET 0x203000 /* PCM */ > +#define SPI0_OFFSET 0x204000 /* SPI master */ > #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ > +#define PIXV0_OFFSET 0x206000 > +#define PIXV1_OFFSET 0x207000 > +#define DPI_OFFSET 0x208000 > +#define DSI0_OFFSET 0x209000 /* Display Serial Interface */ > +#define PWM_OFFSET 0x20c000 > +#define PERM_OFFSET 0x20d000 > +#define TEC_OFFSET 0x20e000 > #define OTP_OFFSET 0x20f000 > +#define SLIM_OFFSET 0x100000 /* SLIMbus */ > +#define CPG_OFFSET 0x110000 > #define AVSP_OFFSET 0x130000 These should be: #define SLIM_OFFSET 0x210000 /* SLIMbus */ #define CPG_OFFSET 0x211000 #define AVSP_OFFSET 0x213000 > #define BSC_SL_OFFSET 0x214000 /* SPI slave */ > +#define THERMAL_OFFSET 0x212000 > #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ > #define EMMC1_OFFSET 0x300000 > +#define EMMC2_OFFSET 0x340000 > +#define HVS_OFFSET 0x400000 > #define SMI_OFFSET 0x600000 > +#define DSI1_OFFSET 0x700000 > +#define UCAM_OFFSET 0x800000 > +#define CMI_OFFSET 0x802000 > #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ > #define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ > +#define VECA_OFFSET 0x806000 > +#define PIXV2_OFFSET 0x807000 > +#define HDMI_OFFSET 0x808000 > +#define HDCP_OFFSET 0x809000 > +#define ARBR0_OFFSET 0x80a000 > #define DBUS_OFFSET 0x900000 > #define AVE0_OFFSET 0x910000 > #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ > +#define V3D_OFFSET 0xc00000 > #define SDRAMC_OFFSET 0xe00000 > +#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */ > +#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */ > +#define ARBR1_OFFSET 0xe04000 > #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ > +#define DCRC_OFFSET 0xe07000 > +#define AXIP_OFFSET 0xe08000 > > /* GPU interrupts */ > #define INTERRUPT_TIMER0 0 >