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* [PATCH 0/7] arm64: zynqmp: DT syncup
@ 2021-05-31  7:59 Michal Simek
  2021-05-31  8:00 ` [PATCH 1/7] arm64: zynqmp: Update psgtr clocks index for boards Michal Simek
                   ` (7 more replies)
  0 siblings, 8 replies; 9+ messages in thread
From: Michal Simek @ 2021-05-31  7:59 UTC (permalink / raw)
  To: u-boot, git; +Cc: Amit Kumar Mahapatra, Michal Simek, Stefano Stabellini

Hi,

I am sending this series to align DT files with the latest description.
Couple of changes are taken from Linux kernel and others from Xilinx trees.

Thanks,
Michal


Michal Simek (6):
  arm64: zynqmp: Update psgtr clocks index for boards
  arm64: zynqmp: Disable CCI by default
  arm64: zynqmp: Add reset description for sata
  arm64: zynqmp: Move DP nodes to the end of file (zcu106)
  arm64: zynqmp: Add label for zynqmp_ipi
  arm64: zynqmp: Update Copyright years to 2021

Stefano Stabellini (1):
  arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi

 arch/arm/dts/zynqmp-zc1232-revA.dts      |  2 +-
 arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts |  2 +-
 arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts |  2 +-
 arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts |  2 +-
 arch/arm/dts/zynqmp-zcu100-revC.dts      | 20 ++++++-------
 arch/arm/dts/zynqmp-zcu102-revA.dts      |  2 +-
 arch/arm/dts/zynqmp-zcu104-revA.dts      |  2 +-
 arch/arm/dts/zynqmp-zcu104-revC.dts      |  2 +-
 arch/arm/dts/zynqmp-zcu106-revA.dts      | 38 ++++++++++++------------
 arch/arm/dts/zynqmp-zcu111-revA.dts      | 16 +++++-----
 arch/arm/dts/zynqmp-zcu1275-revA.dts     |  2 +-
 arch/arm/dts/zynqmp-zcu1275-revB.dts     |  2 +-
 arch/arm/dts/zynqmp-zcu1285-revA.dts     |  2 +-
 arch/arm/dts/zynqmp-zcu208-revA.dts      |  8 ++---
 arch/arm/dts/zynqmp-zcu216-revA.dts      |  8 ++---
 arch/arm/dts/zynqmp.dtsi                 |  8 +++--
 16 files changed, 61 insertions(+), 57 deletions(-)

-- 
2.31.1


^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH 1/7] arm64: zynqmp: Update psgtr clocks index for boards
  2021-05-31  7:59 [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
@ 2021-05-31  8:00 ` Michal Simek
  2021-05-31  8:00 ` [PATCH 2/7] arm64: zynqmp: Disable CCI by default Michal Simek
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2021-05-31  8:00 UTC (permalink / raw)
  To: u-boot, git

Update the psgtr clock indexing for couple of zynqmp boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-zcu100-revC.dts | 18 +++++++++---------
 arch/arm/dts/zynqmp-zcu106-revA.dts | 14 +++++++-------
 arch/arm/dts/zynqmp-zcu111-revA.dts | 14 +++++++-------
 arch/arm/dts/zynqmp-zcu208-revA.dts |  6 +++---
 arch/arm/dts/zynqmp-zcu216-revA.dts |  6 +++---
 5 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index b83696cccd2b..3be69ad9bce4 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -132,13 +132,13 @@
 		io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
 	};
 
-	si5335a_0: clk26 {
+	si5335_0: si5335_0 { /* clk0_usb - u23 */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <26000000>;
 	};
 
-	si5335a_1: clk27 {
+	si5335_1: si5335_1 { /* clk1_dp - u23 */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <27000000>;
@@ -483,13 +483,6 @@
 	};
 };
 
-&psgtr {
-	status = "okay";
-	/* usb3, dps */
-	clocks = <&si5335a_0>, <&si5335a_1>;
-	clock-names = "ref0", "ref1";
-};
-
 &rtc {
 	status = "okay";
 };
@@ -525,6 +518,13 @@
 	};
 };
 
+&psgtr {
+	status = "okay";
+	/* usb3, dp */
+	clocks = <&si5335_0>, <&si5335_1>;
+	clock-names = "ref0", "ref1";
+};
+
 &spi0 { /* Low Speed connector */
 	status = "okay";
 	label = "LS-SPI0";
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index ae20e581c0f4..e86fef5be6f0 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -958,13 +958,6 @@
 	};
 };
 
-&psgtr {
-	status = "okay";
-	/* nc, sata, usb3, dp */
-	clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
-	clock-names = "ref1", "ref2", "ref3";
-};
-
 &qspi {
 	status = "okay";
 	is-dual = <1>;
@@ -995,6 +988,13 @@
 	};
 };
 
+&psgtr {
+	status = "okay";
+	/* nc, sata, usb3, dp */
+	clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+	clock-names = "ref1", "ref2", "ref3";
+};
+
 &rtc {
 	status = "okay";
 };
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index d564f74344c9..10bb45b49f1a 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -773,13 +773,6 @@
 	};
 };
 
-&psgtr {
-	status = "okay";
-	/* nc, sata, usb3, dp */
-	clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
-	clock-names = "ref1", "ref2", "ref3";
-};
-
 &qspi {
 	status = "okay";
 	is-dual = <1>;
@@ -810,6 +803,13 @@
 	};
 };
 
+&psgtr {
+	status = "okay";
+	/* nc, dp, usb3, sata */
+	clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
+	clock-names = "ref1", "ref2", "ref3";
+};
+
 &rtc {
 	status = "okay";
 };
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 880281d4e79b..496e8d1de22b 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -651,9 +651,9 @@
 
 &psgtr {
 	status = "okay";
-	/* pcie, sata, usb3, dp */
-	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
-	clock-names = "ref0", "ref1", "ref2", "ref3";
+	/* nc, nc, usb3, sata */
+	clocks = <&si5341 0 2>, <&si5341 0 3>;
+	clock-names = "ref2", "ref3";
 };
 
 &rtc {
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index f899226ae198..3a205c089444 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -132,9 +132,9 @@
 
 &psgtr {
 	status = "okay";
-	/* pcie, sata, usb3, dp */
-	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
-	clock-names = "ref0", "ref1", "ref2", "ref3";
+	/* nc, nc, usb3, sata */
+	clocks = <&si5341 0 2>, <&si5341 0 3>;
+	clock-names = "ref2", "ref3";
 };
 
 &dcc {
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 2/7] arm64: zynqmp: Disable CCI by default
  2021-05-31  7:59 [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
  2021-05-31  8:00 ` [PATCH 1/7] arm64: zynqmp: Update psgtr clocks index for boards Michal Simek
@ 2021-05-31  8:00 ` Michal Simek
  2021-05-31  8:00 ` [PATCH 3/7] arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi Michal Simek
                   ` (5 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2021-05-31  8:00 UTC (permalink / raw)
  To: u-boot, git; +Cc: Amit Kumar Mahapatra, Michal Simek, Stefano Stabellini

There is no reason to have CCI no enabled by default. Enable it when your
system configuration requires it. In Xilinx configuration flow this is
work for Device Tree Generator which reads information from HW Design
configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 84d9770225aa..db4099b7516b 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -246,6 +246,7 @@
 
 		cci: cci@fd6e0000 {
 			compatible = "arm,cci-400";
+			status = "disabled";
 			reg = <0x0 0xfd6e0000 0x0 0x9000>;
 			ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 			#address-cells = <1>;
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 3/7] arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi
  2021-05-31  7:59 [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
  2021-05-31  8:00 ` [PATCH 1/7] arm64: zynqmp: Update psgtr clocks index for boards Michal Simek
  2021-05-31  8:00 ` [PATCH 2/7] arm64: zynqmp: Disable CCI by default Michal Simek
@ 2021-05-31  8:00 ` Michal Simek
  2021-05-31  8:00 ` [PATCH 4/7] arm64: zynqmp: Add reset description for sata Michal Simek
                   ` (4 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2021-05-31  8:00 UTC (permalink / raw)
  To: u-boot, git; +Cc: Stefano Stabellini, Amit Kumar Mahapatra

From: Stefano Stabellini <stefano.stabellini@xilinx.com>

The SMMU is disabled in device tree so this change has no impact.
The benefit is that this way it is in sync with xen.dtsi. Xen enables
the SMMU and makes use of it.

Signed-off-by: Stefano Stabellini <stefano.stabellini@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index db4099b7516b..37ee9539801c 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -648,6 +648,8 @@
 					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 					<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 					<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x4d0>;
 			power-domains = <&zynqmp_firmware PD_PCIE>;
 			pcie_intc: legacy-interrupt-controller {
 				interrupt-controller;
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 4/7] arm64: zynqmp: Add reset description for sata
  2021-05-31  7:59 [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
                   ` (2 preceding siblings ...)
  2021-05-31  8:00 ` [PATCH 3/7] arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi Michal Simek
@ 2021-05-31  8:00 ` Michal Simek
  2021-05-31  8:00 ` [PATCH 5/7] arm64: zynqmp: Move DP nodes to the end of file (zcu106) Michal Simek
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2021-05-31  8:00 UTC (permalink / raw)
  To: u-boot, git; +Cc: Amit Kumar Mahapatra, Michal Simek, Stefano Stabellini

Sata needs to get reset before configuration that's why add property for it
there.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 37ee9539801c..345ab97e269a 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -701,6 +701,7 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 133 4>;
 			power-domains = <&zynqmp_firmware PD_SATA>;
+			resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
 			#stream-id-cells = <4>;
 			iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 				 <&smmu 0x4c2>, <&smmu 0x4c3>;
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 5/7] arm64: zynqmp: Move DP nodes to the end of file (zcu106)
  2021-05-31  7:59 [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
                   ` (3 preceding siblings ...)
  2021-05-31  8:00 ` [PATCH 4/7] arm64: zynqmp: Add reset description for sata Michal Simek
@ 2021-05-31  8:00 ` Michal Simek
  2021-05-31  8:00 ` [PATCH 6/7] arm64: zynqmp: Add label for zynqmp_ipi Michal Simek
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2021-05-31  8:00 UTC (permalink / raw)
  To: u-boot, git

Just sync it with others for easier comparison.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-zcu106-revA.dts | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index e86fef5be6f0..2fd41ad2d523 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -163,17 +163,6 @@
 	status = "okay";
 };
 
-&zynqmp_dpdma {
-	status = "okay";
-};
-
-&zynqmp_dpsub {
-	status = "okay";
-	phy-names = "dp-phy0", "dp-phy1";
-	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
-	       <&psgtr 0 PHY_TYPE_DP 1 3>;
-};
-
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
 	status = "okay";
@@ -1056,3 +1045,14 @@
 &watchdog0 {
 	status = "okay";
 };
+
+&zynqmp_dpdma {
+	status = "okay";
+};
+
+&zynqmp_dpsub {
+	status = "okay";
+	phy-names = "dp-phy0", "dp-phy1";
+	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+	       <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 6/7] arm64: zynqmp: Add label for zynqmp_ipi
  2021-05-31  7:59 [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
                   ` (4 preceding siblings ...)
  2021-05-31  8:00 ` [PATCH 5/7] arm64: zynqmp: Move DP nodes to the end of file (zcu106) Michal Simek
@ 2021-05-31  8:00 ` Michal Simek
  2021-05-31  8:00 ` [PATCH 7/7] arm64: zynqmp: Update Copyright years to 2021 Michal Simek
  2021-06-10  7:25 ` [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
  7 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2021-05-31  8:00 UTC (permalink / raw)
  To: u-boot, git; +Cc: Amit Kumar Mahapatra, Michal Simek, Stefano Stabellini

Add label which is used by bootloader for adding bootloader specific flag.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3dc8416abdd3498e61edcd83830a12af295c5c6d.1611224800.git.michal.simek@xilinx.com
---

 arch/arm/dts/zynqmp.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 345ab97e269a..deb3fa3ab3f3 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -100,7 +100,7 @@
 		};
 	};
 
-	zynqmp_ipi {
+	zynqmp_ipi: zynqmp_ipi {
 		u-boot,dm-pre-reloc;
 		compatible = "xlnx,zynqmp-ipi-mailbox";
 		interrupt-parent = <&gic>;
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 7/7] arm64: zynqmp: Update Copyright years to 2021
  2021-05-31  7:59 [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
                   ` (5 preceding siblings ...)
  2021-05-31  8:00 ` [PATCH 6/7] arm64: zynqmp: Add label for zynqmp_ipi Michal Simek
@ 2021-05-31  8:00 ` Michal Simek
  2021-06-10  7:25 ` [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
  7 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2021-05-31  8:00 UTC (permalink / raw)
  To: u-boot, git; +Cc: Amit Kumar Mahapatra, Stefano Stabellini

Trivial change for all files I have touched recently.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-zc1232-revA.dts      | 2 +-
 arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +-
 arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +-
 arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 2 +-
 arch/arm/dts/zynqmp-zcu100-revC.dts      | 2 +-
 arch/arm/dts/zynqmp-zcu102-revA.dts      | 2 +-
 arch/arm/dts/zynqmp-zcu104-revA.dts      | 2 +-
 arch/arm/dts/zynqmp-zcu104-revC.dts      | 2 +-
 arch/arm/dts/zynqmp-zcu106-revA.dts      | 2 +-
 arch/arm/dts/zynqmp-zcu111-revA.dts      | 2 +-
 arch/arm/dts/zynqmp-zcu1275-revA.dts     | 2 +-
 arch/arm/dts/zynqmp-zcu1275-revB.dts     | 2 +-
 arch/arm/dts/zynqmp-zcu1285-revA.dts     | 2 +-
 arch/arm/dts/zynqmp-zcu208-revA.dts      | 2 +-
 arch/arm/dts/zynqmp-zcu216-revA.dts      | 2 +-
 arch/arm/dts/zynqmp.dtsi                 | 2 +-
 16 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts
index ef7cf0a36b21..65dd4e1f3a5d 100644
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZC1232
  *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 039a8da1a960..0c6a2a92dfe5 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
  *
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index d6e924803354..1a8cfdeb7f45 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP zc1751-xm016-dc2
  *
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 46b27a000949..41ab20c3895f 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP zc1751-xm019-dc5
  *
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
  * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
  * Michal Simek <michal.simek@xilinx.com>
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 3be69ad9bce4..cad1a23e9539 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU100 revC
  *
- * (C) Copyright 2016 - 2020, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  * Nathalie Chan King Choy
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index ec61b7089da2..7190e876d8dd 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevA
  *
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index c25ac9af48e8..76c635f0d460 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU104
  *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index ce9d8fb3b815..f9eb4caaf8c0 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU104
  *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 2fd41ad2d523..4da7a3edf548 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU106
  *
- * (C) Copyright 2016 - 2020, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 10bb45b49f1a..85821065dd43 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU111
  *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index b9a9d9802d93..10d8bc8f9a19 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU1275
  *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index f14707419b40..97ae1b2d2d71 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU1275 RevB
  *
- * (C) Copyright 2018 - 2020, Xilinx, Inc.
+ * (C) Copyright 2018 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
index 42a73ea31aec..eaf99a9fa82d 100644
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU1285 RevA
  *
- * (C) Copyright 2018 - 2020, Xilinx, Inc.
+ * (C) Copyright 2018 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 496e8d1de22b..03c84ae21acb 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU208
  *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 3a205c089444..fd1d9bfbd199 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU216
  *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index deb3fa3ab3f3..47ffdf1b1650 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP
  *
- * (C) Copyright 2014 - 2020, Xilinx, Inc.
+ * (C) Copyright 2014 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  *
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [PATCH 0/7] arm64: zynqmp: DT syncup
  2021-05-31  7:59 [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
                   ` (6 preceding siblings ...)
  2021-05-31  8:00 ` [PATCH 7/7] arm64: zynqmp: Update Copyright years to 2021 Michal Simek
@ 2021-06-10  7:25 ` Michal Simek
  7 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2021-06-10  7:25 UTC (permalink / raw)
  To: U-Boot, git; +Cc: Amit Kumar Mahapatra, Stefano Stabellini

po 31. 5. 2021 v 10:00 odesílatel Michal Simek <michal.simek@xilinx.com> napsal:
>
> Hi,
>
> I am sending this series to align DT files with the latest description.
> Couple of changes are taken from Linux kernel and others from Xilinx trees.
>
> Thanks,
> Michal
>
>
> Michal Simek (6):
>   arm64: zynqmp: Update psgtr clocks index for boards
>   arm64: zynqmp: Disable CCI by default
>   arm64: zynqmp: Add reset description for sata
>   arm64: zynqmp: Move DP nodes to the end of file (zcu106)
>   arm64: zynqmp: Add label for zynqmp_ipi
>   arm64: zynqmp: Update Copyright years to 2021
>
> Stefano Stabellini (1):
>   arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi
>
>  arch/arm/dts/zynqmp-zc1232-revA.dts      |  2 +-
>  arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts |  2 +-
>  arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts |  2 +-
>  arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts |  2 +-
>  arch/arm/dts/zynqmp-zcu100-revC.dts      | 20 ++++++-------
>  arch/arm/dts/zynqmp-zcu102-revA.dts      |  2 +-
>  arch/arm/dts/zynqmp-zcu104-revA.dts      |  2 +-
>  arch/arm/dts/zynqmp-zcu104-revC.dts      |  2 +-
>  arch/arm/dts/zynqmp-zcu106-revA.dts      | 38 ++++++++++++------------
>  arch/arm/dts/zynqmp-zcu111-revA.dts      | 16 +++++-----
>  arch/arm/dts/zynqmp-zcu1275-revA.dts     |  2 +-
>  arch/arm/dts/zynqmp-zcu1275-revB.dts     |  2 +-
>  arch/arm/dts/zynqmp-zcu1285-revA.dts     |  2 +-
>  arch/arm/dts/zynqmp-zcu208-revA.dts      |  8 ++---
>  arch/arm/dts/zynqmp-zcu216-revA.dts      |  8 ++---
>  arch/arm/dts/zynqmp.dtsi                 |  8 +++--
>  16 files changed, 61 insertions(+), 57 deletions(-)
>
> --
> 2.31.1
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-06-10  7:25 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-31  7:59 [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek
2021-05-31  8:00 ` [PATCH 1/7] arm64: zynqmp: Update psgtr clocks index for boards Michal Simek
2021-05-31  8:00 ` [PATCH 2/7] arm64: zynqmp: Disable CCI by default Michal Simek
2021-05-31  8:00 ` [PATCH 3/7] arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi Michal Simek
2021-05-31  8:00 ` [PATCH 4/7] arm64: zynqmp: Add reset description for sata Michal Simek
2021-05-31  8:00 ` [PATCH 5/7] arm64: zynqmp: Move DP nodes to the end of file (zcu106) Michal Simek
2021-05-31  8:00 ` [PATCH 6/7] arm64: zynqmp: Add label for zynqmp_ipi Michal Simek
2021-05-31  8:00 ` [PATCH 7/7] arm64: zynqmp: Update Copyright years to 2021 Michal Simek
2021-06-10  7:25 ` [PATCH 0/7] arm64: zynqmp: DT syncup Michal Simek

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