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From: Pu Wen <puwen@hygon.cn>
To: xen-devel@lists.xenproject.org
Cc: "Wei Liu" <wei.liu2@citrix.com>,
	"Suravee Suthikulpanit" <suravee.suthikulpanit@amd.com>,
	"Pu Wen" <puwen@hygon.cn>, "Jan Beulich" <jbeulich@suse.com>,
	"Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Boris Ostrovsky" <boris.ostrovsky@oracle.com>,
	"Brian Woods" <brian.woods@amd.com>,
	"Roger Pau Monné" <roger.pau@citrix.com>
Subject: [PATCH v3 03/14] x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU
Date: Mon, 25 Mar 2019 21:30:15 +0800	[thread overview]
Message-ID: <babf13f907b9b85afe40cdffce4ee2cf17f67f11.1553520193.git.puwen@hygon.cn> (raw)
In-Reply-To: <cover.1553520193.git.puwen@hygon.cn>

As Hygon Dhyana CPU share similar PMU architecture with AMD family
17h one, so add Hygon Dhyana support in vpmu_arch_initialise() and
vpmu_init() by sharing AMD code path.

Split the common part in amd_vpmu_init() to a static function
_vpmu_init(), making AMD and Hygon to call the shared function to
initialize vPMU.

As current vPMU still not support Zen(family 17h), add 0x17 support
to amd_vpmu_init().

Also create a function hygon_vpmu_init() for Hygon vPMU initialization.

Both of AMD 17h and Hygon 18h have the same performance event select
and counter MSRs as AMD 15h has, so reuse the 15h definitions for them.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 xen/arch/x86/cpu/vpmu.c     |  5 ++++
 xen/arch/x86/cpu/vpmu_amd.c | 57 ++++++++++++++++++++++++++++++++-------------
 xen/include/asm-x86/vpmu.h  |  1 +
 3 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c
index 8f6daf1..93a27d8 100644
--- a/xen/arch/x86/cpu/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu.c
@@ -456,6 +456,7 @@ static int vpmu_arch_initialise(struct vcpu *v)
     switch ( vendor )
     {
     case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
         ret = svm_vpmu_initialise(v);
         break;
 
@@ -876,6 +877,10 @@ static int __init vpmu_init(void)
         if ( amd_vpmu_init() )
            vpmu_mode = XENPMU_MODE_OFF;
         break;
+    case X86_VENDOR_HYGON:
+        if ( hygon_vpmu_init() )
+           vpmu_mode = XENPMU_MODE_OFF;
+        break;
     case X86_VENDOR_INTEL:
         if ( core2_vpmu_init() )
            vpmu_mode = XENPMU_MODE_OFF;
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index 5efc39b..3fc955f 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -538,13 +538,37 @@ int svm_vpmu_initialise(struct vcpu *v)
     return 0;
 }
 
-int __init amd_vpmu_init(void)
+static int _vpmu_init(void)
 {
     unsigned int i;
 
+    if ( sizeof(struct xen_pmu_data) +
+         2 * sizeof(uint64_t) * num_counters > PAGE_SIZE )
+    {
+        printk(XENLOG_WARNING
+               "VPMU: Register bank does not fit into VPMU shared page\n");
+        counters = ctrls = NULL;
+        num_counters = 0;
+        return -ENOSPC;
+    }
+
+    for ( i = 0; i < num_counters; i++ )
+    {
+        rdmsrl(ctrls[i], ctrl_rsvd[i]);
+        ctrl_rsvd[i] &= CTRL_RSVD_MASK;
+    }
+
+    regs_sz = 2 * sizeof(uint64_t) * num_counters;
+
+    return 0;
+}
+
+int __init amd_vpmu_init(void)
+{
     switch ( current_cpu_data.x86 )
     {
     case 0x15:
+    case 0x17:
         num_counters = F15H_NUM_COUNTERS;
         counters = AMD_F15H_COUNTERS;
         ctrls = AMD_F15H_CTRLS;
@@ -565,24 +589,25 @@ int __init amd_vpmu_init(void)
         return -EINVAL;
     }
 
-    if ( sizeof(struct xen_pmu_data) +
-         2 * sizeof(uint64_t) * num_counters > PAGE_SIZE )
-    {
-        printk(XENLOG_WARNING
-               "VPMU: Register bank does not fit into VPMU shared page\n");
-        counters = ctrls = NULL;
-        num_counters = 0;
-        return -ENOSPC;
-    }
+    return _vpmu_init();
+}
 
-    for ( i = 0; i < num_counters; i++ )
+int __init hygon_vpmu_init(void)
+{
+    switch ( current_cpu_data.x86 )
     {
-        rdmsrl(ctrls[i], ctrl_rsvd[i]);
-        ctrl_rsvd[i] &= CTRL_RSVD_MASK;
+    case 0x18:
+        num_counters = F15H_NUM_COUNTERS;
+        counters = AMD_F15H_COUNTERS;
+        ctrls = AMD_F15H_CTRLS;
+        k7_counters_mirrored = 1;
+        break;
+    default:
+        printk(XENLOG_WARNING "VPMU: Unsupported CPU family %#x\n",
+               current_cpu_data.x86);
+        return -EINVAL;
     }
 
-    regs_sz = 2 * sizeof(uint64_t) * num_counters;
-
-    return 0;
+    return _vpmu_init();
 }
 
diff --git a/xen/include/asm-x86/vpmu.h b/xen/include/asm-x86/vpmu.h
index 1287b9f..55f85ba 100644
--- a/xen/include/asm-x86/vpmu.h
+++ b/xen/include/asm-x86/vpmu.h
@@ -52,6 +52,7 @@ struct arch_vpmu_ops {
 int core2_vpmu_init(void);
 int vmx_vpmu_initialise(struct vcpu *);
 int amd_vpmu_init(void);
+int hygon_vpmu_init(void);
 int svm_vpmu_initialise(struct vcpu *);
 
 struct vpmu_struct {
-- 
2.7.4


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  parent reply	other threads:[~2019-03-25 13:40 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-25 13:29 [PATCH v3 00/14] Add support for Hygon Dhyana Family 18h processor Pu Wen
2019-03-25 13:29 ` [PATCH v3 01/14] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
2019-03-26 15:48   ` Jan Beulich
2019-03-27  8:14     ` Pu Wen
2019-03-27  8:30       ` Jan Beulich
2019-03-27 10:08         ` Pu Wen
2019-03-25 13:30 ` [PATCH v3 02/14] x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2 Pu Wen
2019-03-25 13:30 ` Pu Wen [this message]
2019-03-26 16:10   ` [PATCH v3 03/14] x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU Jan Beulich
2019-03-27  8:16     ` Pu Wen
2019-03-27  8:37       ` Jan Beulich
2019-03-27 10:08         ` Pu Wen
2019-03-25 13:30 ` [PATCH v3 04/14] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure Pu Wen
2019-03-25 13:30 ` [PATCH v3 05/14] x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery Pu Wen
2019-03-25 13:30 ` [PATCH v3 06/14] x86/apic: Add Hygon Dhyana support Pu Wen
2019-03-25 13:30 ` [PATCH v3 07/14] x86/acpi: " Pu Wen
2019-03-25 13:31 ` [PATCH v3 08/14] x86/iommu: " Pu Wen
2019-03-25 13:31 ` [PATCH v3 09/14] x86/pv: Add Hygon Dhyana support to emulate MSRs access Pu Wen
2019-03-25 13:31 ` [PATCH v3 10/14] x86/domain: Add Hygon Dhyana support Pu Wen
2019-03-25 13:31 ` [PATCH v3 11/14] x86/domctl: " Pu Wen
2019-03-25 13:31 ` [PATCH v3 12/14] x86/traps: " Pu Wen
2019-03-25 13:32 ` [PATCH v3 13/14] x86/cpuid: " Pu Wen
2019-03-25 13:32 ` [PATCH v3 14/14] tools/libxc: " Pu Wen

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