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Fri, 16 Jun 2023 09:48:19 +0000 (GMT) Message-ID: Date: Fri, 16 Jun 2023 15:18:17 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v4 1/6] target/ppc: Fix instruction loading endianness in alignment interrupt Content-Language: en-US To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Daniel Henrique Barboza , harshpb@linux.ibm.com References: <20230530132543.385138-2-npiggin@gmail.com> <0bbbffa7-d66c-66f2-f660-321e4f8aa026@linux.vnet.ibm.com> From: Anushree Mathur In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: j9A0csFnlBQ46hMs4H2g6ZJWDDPP3Uaz X-Proofpoint-ORIG-GUID: XaN4qxl9nMlXnZeorrRm4XLlhrq2LMCZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-16_06,2023-06-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 adultscore=0 clxscore=1015 suspectscore=0 mlxlogscore=857 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306160085 Received-SPF: none client-ip=148.163.158.5; envelope-from=anushree.mathur@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.098, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/15/23 08:21, Nicholas Piggin wrote: > On Wed Jun 14, 2023 at 3:51 PM AEST, Anushree Mathur wrote: >> On 5/30/23 18:55, Nicholas Piggin wrote: >>> powerpc ifetch endianness depends on MSR[LE] so it has to byteswap >>> after cpu_ldl_code(). This corrects DSISR bits in alignment >>> interrupts when running in little endian mode. >>> >>> Reviewed-by: Fabiano Rosas >>> Signed-off-by: Nicholas Piggin >>> --- >>> target/ppc/excp_helper.c | 22 +++++++++++++++++++++- >>> 1 file changed, 21 insertions(+), 1 deletion(-) >>> >>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c >>> index c13f2afa04..0274617b4a 100644 >>> --- a/target/ppc/excp_helper.c >>> +++ b/target/ppc/excp_helper.c >>> @@ -133,6 +133,26 @@ static void dump_hcall(CPUPPCState *env) >>> env->nip); >>> } >>> >>> +#ifdef CONFIG_TCG >>> +/* Return true iff byteswap is needed in a scalar memop */ >>> +static inline bool need_byteswap(CPUArchState *env) >>> +{ >>> + /* SOFTMMU builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is set */ >>> + return !!(env->msr & ((target_ulong)1 << MSR_LE)); >>> +} >>> + >>> +static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr) >> This hunk fails to compile with configure --disable-tcg > I don't see how since it's inside CONFIG_TCG. Seems to work here. > You don't have an old version of the patch applied? > > What configure options exactly? > > Thanks, > Nick The configure options i used are: ./configure --target-list=ppc64-softmmu --disable-tcg --prefix=/usr I applied the latest patches but still i was seeing the same issue. Can you check this once! Thanks, Anushree-Mathur