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[124.171.83.152]) by smtp.gmail.com with ESMTPSA id j14sm11252447pjz.21.2020.09.07.20.18.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Sep 2020 20:18:51 -0700 (PDT) Subject: Re: [PATCH v1 02/10] powerpc/kernel/iommu: Align size for IOMMU_PAGE_SIZE on iommu_*_coherent() To: Leonardo Bras , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Christophe Leroy , Joel Stanley , Thiago Jung Bauermann , Ram Pai , Brian King , Murilo Fossa Vicentini , David Dai Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org References: <20200817234033.442511-1-leobras.c@gmail.com> <20200817234033.442511-3-leobras.c@gmail.com> <7b9640e0-568f-1470-40f4-a3ccec8abcf2@ozlabs.ru> <2aacd45f047489642da1731c92d3555ad101e3c7.camel@gmail.com> <81f106bd-8962-22f2-f14a-378d3486f57e@ozlabs.ru> <39ad3a9c103faf9c5fc2fd5700d8606eb4a2b67e.camel@gmail.com> <8f569f68-5145-676e-50a1-b13f3fbd69cc@ozlabs.ru> From: Alexey Kardashevskiy Message-ID: Date: Tue, 8 Sep 2020 13:18:44 +1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/09/2020 16:04, Leonardo Bras wrote: > On Thu, 2020-09-03 at 14:41 +1000, Alexey Kardashevskiy wrote: >> I am new to this, so I am trying to understand how a memory page mapped >>> as DMA, and used for something else could be a problem. >> >> From the device prospective, there is PCI space and everything from 0 >> till 1<<64 is accessible and what is that mapped to - the device does >> not know. PHB's IOMMU is the thing to notice invalid access and raise >> EEH but PHB only knows about PCI->physical memory mapping (with IOMMU >> pages) but nothing about the host kernel pages. Does this help? Thanks, > > According to our conversation on Slack: > 1- There is a problem if a hypervisor gives to it's VMs contiguous > memory blocks that are not aligned to IOMMU pages, because then an > iommu_map_page() could map some memory in this VM and some memory in > other VM / process. > 2- To guarantee this, we should have system pagesize >= iommu_pagesize > > One way to get (2) is by doing this in enable_ddw(): > if ((query.page_size & 4) && PAGE_SHIFT >= 24) { You won't ever (well, soon) see PAGE_SHIFT==24, it is either 4K or 64K. However 16MB IOMMU pages is fine - if hypervisor uses huge pages for VMs RAM, it also then advertises huge IOMMU pages in ddw-query. So for the 1:1 case there must be no "PAGE_SHIFT >= 24". > page_shift = 24; /* 16MB */ > } else if ((query.page_size & 2) && PAGE_SHIFT >= 16 ) { > page_shift = 16; /* 64kB */ > } else if (query.page_size & 1 && PAGE_SHIFT >= 12) { > page_shift = 12; /* 4kB */ > [...] > > Another way of solving this, would be adding in LoPAR documentation > that the blocksize of contiguous memory the hypervisor gives a VM > should always be aligned to IOMMU pagesize offered. I think this is assumed already by the design of the DDW API. > > I think the best approach would be first sending the above patch, which > is faster, and then get working into adding that to documentation, so > hypervisors guarantee this. > > If this gets into the docs, we can revert the patch. > > What do you think? I think we diverted from the original patch :) I am not quite sure what you were fixing there. Thanks, -- Alexey