From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB12FC433F5 for ; Thu, 25 Nov 2021 20:30:42 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 5F9554B0FB; Thu, 25 Nov 2021 15:30:42 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@redhat.com Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LpyJ+Sj8enXb; Thu, 25 Nov 2021 15:30:41 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 0996C4B13E; Thu, 25 Nov 2021 15:30:41 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E6CDF4B129 for ; Thu, 25 Nov 2021 15:30:38 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1PnjNUdVZa0R for ; Thu, 25 Nov 2021 15:30:37 -0500 (EST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6C0034B0FB for ; Thu, 25 Nov 2021 15:30:37 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1637872237; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iNfrKVVQE1EpKSUQXL266KgcPgP5LAHIUbP4H9pnx5A=; b=ebICdqRSIK7neFdEfX6JqV/YtnbFDSRT6xa+LGGwKLw9N3BLAu98yuL9ZVFwUNwZ1I6Czz o9TJn9+VnIjMZd3LH5FEe6yl3vTkZH2KNbr00Pg3zGAe3Qw/tkxDWVSHoV3K2wxv+FOHgy 9NE/OaSlxZwuR6XCj0DOsyF2zDzqDJY= Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-536-igyTGAixMtiQKT01quEiXQ-1; Thu, 25 Nov 2021 15:30:33 -0500 X-MC-Unique: igyTGAixMtiQKT01quEiXQ-1 Received: by mail-wm1-f70.google.com with SMTP id o18-20020a05600c511200b00332fa17a02eso4066492wms.5 for ; Thu, 25 Nov 2021 12:30:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=iNfrKVVQE1EpKSUQXL266KgcPgP5LAHIUbP4H9pnx5A=; b=ir2Kxct8cbuT/XEJNQ6IjRK8WHSZ0ZHdpSsW4VzMM0IRdWx+kBrCdSHvqeLvW8yBUB rJgJE4LgjuI7XSfhsx4c543dFnOzAK7f1daVEpp6S6ttWTzhad21nCAkFF4d72udynFT A8SCOZSz+MVxO26ZAf8N9zdCGskFXTREigCLTGqiFVDMiXL6JM9+zkcH1AI/UDQRXpBs DIfsTuE6siCYASFTyxpRvzQZgpt/DVUCYLJw5jV6aoXWoaNTJ85rKu6/JWPCN1v+2awY Hr7tZzZ2yjnxiQR54l/0ETRKLhvDacZgS1Gpt3HeHAkNGI6DuS4husyCql0S5eK/9K6d LG5g== X-Gm-Message-State: AOAM532qWxfZhJ8kfGT/58EizlQl80ZllAGM036Trh9n/L1GP89pNfLP 0mom9Siov3tgqbWVzOGo0vFvpUsXSPmfoO3Gr/sVpnQdwoDXnIhlRBq+2Yd+2+gb//8NHTydGMO 0hH9EGQC9fKMq3R+C6Bt46ACT X-Received: by 2002:a05:600c:4e4a:: with SMTP id e10mr11046002wmq.155.1637872232475; Thu, 25 Nov 2021 12:30:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJxpB9Sne6bt528o4LNrZerhkHTAF8WsnuzTgtVSd8aKZYeAIsgjjsTr9RNNaL6WNzAIXffHmw== X-Received: by 2002:a05:600c:4e4a:: with SMTP id e10mr11045959wmq.155.1637872232202; Thu, 25 Nov 2021 12:30:32 -0800 (PST) Received: from ?IPv6:2a01:e0a:59e:9d80:527b:9dff:feef:3874? ([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id h27sm10008150wmc.43.2021.11.25.12.30.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Nov 2021 12:30:31 -0800 (PST) Subject: Re: [RFC PATCH v3 10/29] KVM: arm64: Make ID_AA64DFR0_EL1 writable To: Reiji Watanabe , Marc Zyngier , kvmarm@lists.cs.columbia.edu References: <20211117064359.2362060-1-reijiw@google.com> <20211117064359.2362060-11-reijiw@google.com> From: Eric Auger Message-ID: Date: Thu, 25 Nov 2021 21:30:29 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <20211117064359.2362060-11-reijiw@google.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eauger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Cc: Peter Shier , Will Deacon , linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Paolo Bonzini X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Reiji, On 11/17/21 7:43 AM, Reiji Watanabe wrote: > This patch adds id_reg_info for ID_AA64DFR0_EL1 to make it writable > by userspace. > > Return an error if userspace tries to set PMUVER field of the > register to a value that conflicts with the PMU configuration. > > Since number of context-aware breakpoints must be no more than number > of supported breakpoints according to Arm ARM, return an error > if userspace tries to set CTX_CMPS field to such value. > > Signed-off-by: Reiji Watanabe > --- > arch/arm64/kvm/sys_regs.c | 84 ++++++++++++++++++++++++++++++++++----- > 1 file changed, 73 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 772e3d3067b2..0faf458b0efb 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -626,6 +626,45 @@ static int validate_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, > return 0; > } > > +static bool id_reg_has_pmu(u64 val, u64 shift, unsigned int min) I would rename the function as the name currently is misleading. The function validate the val filed @shift againt @min > +{ > + unsigned int pmu = cpuid_feature_extract_unsigned_field(val, shift); > + > + /* > + * Treat IMPLEMENTATION DEFINED functionality as unimplemented for > + * ID_AA64DFR0_EL1.PMUVer/ID_DFR0_EL1.PerfMon. > + */ > + if (pmu == 0xf) > + pmu = 0; Shouldn't we simply forbid the userspace to set 0xF? > + > + return (pmu >= min); > +} > + > +static int validate_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > + const struct id_reg_info *id_reg, u64 val) > +{ > + unsigned int brps, ctx_cmps; > + bool vcpu_pmu, dfr0_pmu; > + > + brps = cpuid_feature_extract_unsigned_field(val, ID_AA64DFR0_BRPS_SHIFT); > + ctx_cmps = cpuid_feature_extract_unsigned_field(val, ID_AA64DFR0_CTX_CMPS_SHIFT); > + > + /* > + * Number of context-aware breakpoints can be no more than number of > + * supported breakpoints. > + */ > + if (ctx_cmps > brps) > + return -EINVAL; > + > + vcpu_pmu = kvm_vcpu_has_pmu(vcpu); > + dfr0_pmu = id_reg_has_pmu(val, ID_AA64DFR0_PMUVER_SHIFT, ID_AA64DFR0_PMUVER_8_0); > + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */ > + if (vcpu_pmu ^ dfr0_pmu) > + return -EPERM; > + > + return 0; > +} > + > static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg) > { > u64 limit = id_reg->vcpu_limit_val; > @@ -669,6 +708,23 @@ static void init_id_aa64isar1_el1_info(struct id_reg_info *id_reg) > id_reg->vcpu_limit_val &= ~PTRAUTH_MASK; > } > > +static void init_id_aa64dfr0_el1_info(struct id_reg_info *id_reg) > +{ > + u64 limit = id_reg->vcpu_limit_val; > + > + /* Limit guests to PMUv3 for ARMv8.4 */ > + limit = cpuid_feature_cap_perfmon_field(limit, ID_AA64DFR0_PMUVER_SHIFT, > + ID_AA64DFR0_PMUVER_8_4); > + /* Limit debug to ARMv8.0 */ > + limit &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); > + limit |= (FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6)); > + > + /* Hide SPE from guests */ > + limit &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); > + > + id_reg->vcpu_limit_val = limit; > +} > + > static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, > const struct id_reg_info *idr) > { > @@ -698,6 +754,14 @@ static u64 get_reset_id_aa64isar1_el1(struct kvm_vcpu *vcpu, > idr->vcpu_limit_val : (idr->vcpu_limit_val & ~PTRAUTH_MASK); > } > > +static u64 get_reset_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > + const struct id_reg_info *idr) > +{ > + return kvm_vcpu_has_pmu(vcpu) ? > + idr->vcpu_limit_val : > + (idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER))); > +} > + > static struct id_reg_info id_aa64pfr0_el1_info = { > .sys_reg = SYS_ID_AA64PFR0_EL1, > .ftr_check_types = S_FCT(ID_AA64PFR0_ASIMD_SHIFT, FCT_LOWER_SAFE) | > @@ -742,6 +806,14 @@ static struct id_reg_info id_aa64mmfr0_el1_info = { > .validate = validate_id_aa64mmfr0_el1, > }; > > +static struct id_reg_info id_aa64dfr0_el1_info = { > + .sys_reg = SYS_ID_AA64DFR0_EL1, > + .ftr_check_types = S_FCT(ID_AA64DFR0_DOUBLELOCK_SHIFT, FCT_LOWER_SAFE), > + .init = init_id_aa64dfr0_el1_info, > + .validate = validate_id_aa64dfr0_el1, > + .get_reset_val = get_reset_id_aa64dfr0_el1, > +}; > + > /* > * An ID register that needs special handling to control the value for the > * guest must have its own id_reg_info in id_reg_info_table. > @@ -753,6 +825,7 @@ static struct id_reg_info id_aa64mmfr0_el1_info = { > static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = { > [IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info, > [IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info, > + [IDREG_IDX(SYS_ID_AA64DFR0_EL1)] = &id_aa64dfr0_el1_info, > [IDREG_IDX(SYS_ID_AA64ISAR0_EL1)] = &id_aa64isar0_el1_info, > [IDREG_IDX(SYS_ID_AA64ISAR1_EL1)] = &id_aa64isar1_el1_info, > [IDREG_IDX(SYS_ID_AA64MMFR0_EL1)] = &id_aa64mmfr0_el1_info, > @@ -1604,17 +1677,6 @@ static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id) > val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), gic_lim); > } > break; > - case SYS_ID_AA64DFR0_EL1: > - /* Limit debug to ARMv8.0 */ > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6); > - /* Limit guests to PMUv3 for ARMv8.4 */ > - val = cpuid_feature_cap_perfmon_field(val, > - ID_AA64DFR0_PMUVER_SHIFT, > - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); > - /* Hide SPE from guests */ > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); > - break; > case SYS_ID_DFR0_EL1: > /* Limit guests to PMUv3 for ARMv8.4 */ > val = cpuid_feature_cap_perfmon_field(val, > Eric _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3011C433EF for ; Thu, 25 Nov 2021 20:32:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=JjzABjT9zFjG8+SuCJpXeaNWfpvuL6qlhN7DGBtjvow=; b=EkM/4IjrimD1F01iz3hXqnZhU4 9uYUQxuGmom5LDnuHWFg45QPp+YLYdxRbwFXckpH+PjHwdyuOrpI5Hb6Vqd2oPwHsPXd+8twR2bjP pr8gdZGtFT2nqHlDcx2Mtl4BCCdI2uzpNBFUbPzWHp3T69LPxiAHlRGtqYXMlW6DlJqjCti3jHrTc 6pvKFyi8Pww7Cyv7bnMUmfexlWwpxh8N7svv6rXk8bG1JTA52E5/3UpvaSDhooXcb2A/cROlAF3rR UH3cO1DCkjcLguV6/QsNEbOdDYgUNxEl4fyvveoL2qvGx8Z0vHUXrDVwafq9ybscX+q0eMPfZUW9J VmfkBfKg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqLOC-008b0c-PM; Thu, 25 Nov 2021 20:30:40 +0000 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqLO9-008b02-8P for linux-arm-kernel@lists.infradead.org; Thu, 25 Nov 2021 20:30:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1637872235; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iNfrKVVQE1EpKSUQXL266KgcPgP5LAHIUbP4H9pnx5A=; b=WBp68Dhk8Zr83ZE6kfPgWuN18VooJgKT1wOV1JRC9m+uzSFqPOgEYpE/u0bHIDtScEX3To Z3U6uO321cMBlrJ9LAPjrAecWsaT17wIgf912vn2IuoFjekqDqw8gr/B66RRTGJu3TUy/P mqHFFr2Os1ZA++2pxTGj7VYisWSIltw= Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-230-ZVWrDIpkNfWzTJMO4bJ9aw-1; Thu, 25 Nov 2021 15:30:34 -0500 X-MC-Unique: ZVWrDIpkNfWzTJMO4bJ9aw-1 Received: by mail-wm1-f72.google.com with SMTP id l6-20020a05600c4f0600b0033321934a39so4058322wmq.9 for ; Thu, 25 Nov 2021 12:30:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=iNfrKVVQE1EpKSUQXL266KgcPgP5LAHIUbP4H9pnx5A=; b=0UPRI3By0PJ7rGTy6FPYDOPbhM3OdZeRv1koha99Ds0sA9vh7KnOfrdTzDVXsNIiik +ajCTAil8x3yWaA/nxZOIwS2FBjQ9rSsit2L6ePK2AHXLw1sQm67HCRaALNmc2sDPkd8 mZUIP9JGvwHOPTsbVuGgf5OOEUvYRkw+vetExG72m3rh1jFZUkydluukq3+ht8IZ6c/A Q4dPehoesFeA/toH5fvIGxRQVXk+x0L0VbUcaUAnUN96kVm2RtwSgs4CjDNDOkhc/Gui ayiCmL8lpXpq0ONeK6xXQ6sbk8kuMkRpkT5eXne7Z80eUl8jlHTc94VX/3qDCoMgv0js WKGA== X-Gm-Message-State: AOAM530rHEdu0IQHwGthKbkE4BvOL4x/MHB5C/tGF2JCFu9jYvTANBgg xmcaRBTvrPL83xuyDrPb7QXfxig55CxWI/OJk2KhUinVJ+INZLfSqYypLKRyy8mtxCC6E39gokD fJWWIFEEa/CYb8AoLoVCRwVGuqxJbSqgQeaHOSOuelhIvOE7kZ9Eg2staK0JUQCut33B2KMg2wL E2rjm5iUUi X-Received: by 2002:a05:600c:4e4a:: with SMTP id e10mr11046015wmq.155.1637872232552; Thu, 25 Nov 2021 12:30:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJxpB9Sne6bt528o4LNrZerhkHTAF8WsnuzTgtVSd8aKZYeAIsgjjsTr9RNNaL6WNzAIXffHmw== X-Received: by 2002:a05:600c:4e4a:: with SMTP id e10mr11045959wmq.155.1637872232202; Thu, 25 Nov 2021 12:30:32 -0800 (PST) Received: from ?IPv6:2a01:e0a:59e:9d80:527b:9dff:feef:3874? ([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id h27sm10008150wmc.43.2021.11.25.12.30.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Nov 2021 12:30:31 -0800 (PST) Subject: Re: [RFC PATCH v3 10/29] KVM: arm64: Make ID_AA64DFR0_EL1 writable To: Reiji Watanabe , Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Will Deacon , Peter Shier , Paolo Bonzini , linux-arm-kernel@lists.infradead.org References: <20211117064359.2362060-1-reijiw@google.com> <20211117064359.2362060-11-reijiw@google.com> From: Eric Auger Message-ID: Date: Thu, 25 Nov 2021 21:30:29 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <20211117064359.2362060-11-reijiw@google.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eauger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211125_123037_420170_5B06AB1E X-CRM114-Status: GOOD ( 30.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Reiji, On 11/17/21 7:43 AM, Reiji Watanabe wrote: > This patch adds id_reg_info for ID_AA64DFR0_EL1 to make it writable > by userspace. > > Return an error if userspace tries to set PMUVER field of the > register to a value that conflicts with the PMU configuration. > > Since number of context-aware breakpoints must be no more than number > of supported breakpoints according to Arm ARM, return an error > if userspace tries to set CTX_CMPS field to such value. > > Signed-off-by: Reiji Watanabe > --- > arch/arm64/kvm/sys_regs.c | 84 ++++++++++++++++++++++++++++++++++----- > 1 file changed, 73 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 772e3d3067b2..0faf458b0efb 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -626,6 +626,45 @@ static int validate_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, > return 0; > } > > +static bool id_reg_has_pmu(u64 val, u64 shift, unsigned int min) I would rename the function as the name currently is misleading. The function validate the val filed @shift againt @min > +{ > + unsigned int pmu = cpuid_feature_extract_unsigned_field(val, shift); > + > + /* > + * Treat IMPLEMENTATION DEFINED functionality as unimplemented for > + * ID_AA64DFR0_EL1.PMUVer/ID_DFR0_EL1.PerfMon. > + */ > + if (pmu == 0xf) > + pmu = 0; Shouldn't we simply forbid the userspace to set 0xF? > + > + return (pmu >= min); > +} > + > +static int validate_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > + const struct id_reg_info *id_reg, u64 val) > +{ > + unsigned int brps, ctx_cmps; > + bool vcpu_pmu, dfr0_pmu; > + > + brps = cpuid_feature_extract_unsigned_field(val, ID_AA64DFR0_BRPS_SHIFT); > + ctx_cmps = cpuid_feature_extract_unsigned_field(val, ID_AA64DFR0_CTX_CMPS_SHIFT); > + > + /* > + * Number of context-aware breakpoints can be no more than number of > + * supported breakpoints. > + */ > + if (ctx_cmps > brps) > + return -EINVAL; > + > + vcpu_pmu = kvm_vcpu_has_pmu(vcpu); > + dfr0_pmu = id_reg_has_pmu(val, ID_AA64DFR0_PMUVER_SHIFT, ID_AA64DFR0_PMUVER_8_0); > + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */ > + if (vcpu_pmu ^ dfr0_pmu) > + return -EPERM; > + > + return 0; > +} > + > static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg) > { > u64 limit = id_reg->vcpu_limit_val; > @@ -669,6 +708,23 @@ static void init_id_aa64isar1_el1_info(struct id_reg_info *id_reg) > id_reg->vcpu_limit_val &= ~PTRAUTH_MASK; > } > > +static void init_id_aa64dfr0_el1_info(struct id_reg_info *id_reg) > +{ > + u64 limit = id_reg->vcpu_limit_val; > + > + /* Limit guests to PMUv3 for ARMv8.4 */ > + limit = cpuid_feature_cap_perfmon_field(limit, ID_AA64DFR0_PMUVER_SHIFT, > + ID_AA64DFR0_PMUVER_8_4); > + /* Limit debug to ARMv8.0 */ > + limit &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); > + limit |= (FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6)); > + > + /* Hide SPE from guests */ > + limit &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); > + > + id_reg->vcpu_limit_val = limit; > +} > + > static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, > const struct id_reg_info *idr) > { > @@ -698,6 +754,14 @@ static u64 get_reset_id_aa64isar1_el1(struct kvm_vcpu *vcpu, > idr->vcpu_limit_val : (idr->vcpu_limit_val & ~PTRAUTH_MASK); > } > > +static u64 get_reset_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > + const struct id_reg_info *idr) > +{ > + return kvm_vcpu_has_pmu(vcpu) ? > + idr->vcpu_limit_val : > + (idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER))); > +} > + > static struct id_reg_info id_aa64pfr0_el1_info = { > .sys_reg = SYS_ID_AA64PFR0_EL1, > .ftr_check_types = S_FCT(ID_AA64PFR0_ASIMD_SHIFT, FCT_LOWER_SAFE) | > @@ -742,6 +806,14 @@ static struct id_reg_info id_aa64mmfr0_el1_info = { > .validate = validate_id_aa64mmfr0_el1, > }; > > +static struct id_reg_info id_aa64dfr0_el1_info = { > + .sys_reg = SYS_ID_AA64DFR0_EL1, > + .ftr_check_types = S_FCT(ID_AA64DFR0_DOUBLELOCK_SHIFT, FCT_LOWER_SAFE), > + .init = init_id_aa64dfr0_el1_info, > + .validate = validate_id_aa64dfr0_el1, > + .get_reset_val = get_reset_id_aa64dfr0_el1, > +}; > + > /* > * An ID register that needs special handling to control the value for the > * guest must have its own id_reg_info in id_reg_info_table. > @@ -753,6 +825,7 @@ static struct id_reg_info id_aa64mmfr0_el1_info = { > static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = { > [IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info, > [IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info, > + [IDREG_IDX(SYS_ID_AA64DFR0_EL1)] = &id_aa64dfr0_el1_info, > [IDREG_IDX(SYS_ID_AA64ISAR0_EL1)] = &id_aa64isar0_el1_info, > [IDREG_IDX(SYS_ID_AA64ISAR1_EL1)] = &id_aa64isar1_el1_info, > [IDREG_IDX(SYS_ID_AA64MMFR0_EL1)] = &id_aa64mmfr0_el1_info, > @@ -1604,17 +1677,6 @@ static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id) > val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), gic_lim); > } > break; > - case SYS_ID_AA64DFR0_EL1: > - /* Limit debug to ARMv8.0 */ > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6); > - /* Limit guests to PMUv3 for ARMv8.4 */ > - val = cpuid_feature_cap_perfmon_field(val, > - ID_AA64DFR0_PMUVER_SHIFT, > - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); > - /* Hide SPE from guests */ > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); > - break; > case SYS_ID_DFR0_EL1: > /* Limit guests to PMUv3 for ARMv8.4 */ > val = cpuid_feature_cap_perfmon_field(val, > Eric _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 161E2C433EF for ; Thu, 25 Nov 2021 20:32:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356931AbhKYUfr (ORCPT ); Thu, 25 Nov 2021 15:35:47 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]:55617 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357035AbhKYUdr (ORCPT ); Thu, 25 Nov 2021 15:33:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1637872235; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iNfrKVVQE1EpKSUQXL266KgcPgP5LAHIUbP4H9pnx5A=; b=WBp68Dhk8Zr83ZE6kfPgWuN18VooJgKT1wOV1JRC9m+uzSFqPOgEYpE/u0bHIDtScEX3To Z3U6uO321cMBlrJ9LAPjrAecWsaT17wIgf912vn2IuoFjekqDqw8gr/B66RRTGJu3TUy/P mqHFFr2Os1ZA++2pxTGj7VYisWSIltw= Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-107--2Ppii6jNdmyFxxds1SU8g-1; Thu, 25 Nov 2021 15:30:33 -0500 X-MC-Unique: -2Ppii6jNdmyFxxds1SU8g-1 Received: by mail-wm1-f69.google.com with SMTP id l4-20020a05600c1d0400b00332f47a0fa3so4062083wms.8 for ; Thu, 25 Nov 2021 12:30:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=iNfrKVVQE1EpKSUQXL266KgcPgP5LAHIUbP4H9pnx5A=; b=vQRRP4SV9nt1Hxq6+sVfdqw/ToTaOe0v6sK8vh92P0MkXxPGLbASFtDmBTCSZrpH5B oztRNIzMHN+0xjRIVdRt8EnYsmtw0PX2WRgx8QzRLpI79lHhQyLRw5kdYXVtmDZvJN51 XnSgsezTAyTYa7Npm0BGKHQeSXccMy0qL5jsZna4Q185HzvOluAY7dbZs9KhPZsCjM7r lZzHn9Q5/Gc6ZXbNxskDqfGnMZEcyPDMzbwSEK9QXcIRMnVdWV+VbGTk0O69xDDupEIF xH+4MWtQ/gyc/9uczcl51Unq6CmS033prsHUx0mIHt0TebSwObGHhz2fHj+1UfKhisWu y1NQ== X-Gm-Message-State: AOAM532LCeqKZrTMUzt9wphqA3ohn+/fhjRZa5GbGtkw5IZngMyRmpz9 1oTC39ZrGfxuU1jD4+RzykCvDLMGBQRbTdlFgq9+kmHF5HCU0D5m57x45OxbO8NrROJf2INKRgs b7TUZzLuFxMao X-Received: by 2002:a05:600c:4e4a:: with SMTP id e10mr11045998wmq.155.1637872232464; Thu, 25 Nov 2021 12:30:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJxpB9Sne6bt528o4LNrZerhkHTAF8WsnuzTgtVSd8aKZYeAIsgjjsTr9RNNaL6WNzAIXffHmw== X-Received: by 2002:a05:600c:4e4a:: with SMTP id e10mr11045959wmq.155.1637872232202; Thu, 25 Nov 2021 12:30:32 -0800 (PST) Received: from ?IPv6:2a01:e0a:59e:9d80:527b:9dff:feef:3874? ([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id h27sm10008150wmc.43.2021.11.25.12.30.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Nov 2021 12:30:31 -0800 (PST) Subject: Re: [RFC PATCH v3 10/29] KVM: arm64: Make ID_AA64DFR0_EL1 writable To: Reiji Watanabe , Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Will Deacon , Peter Shier , Paolo Bonzini , linux-arm-kernel@lists.infradead.org References: <20211117064359.2362060-1-reijiw@google.com> <20211117064359.2362060-11-reijiw@google.com> From: Eric Auger Message-ID: Date: Thu, 25 Nov 2021 21:30:29 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <20211117064359.2362060-11-reijiw@google.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Reiji, On 11/17/21 7:43 AM, Reiji Watanabe wrote: > This patch adds id_reg_info for ID_AA64DFR0_EL1 to make it writable > by userspace. > > Return an error if userspace tries to set PMUVER field of the > register to a value that conflicts with the PMU configuration. > > Since number of context-aware breakpoints must be no more than number > of supported breakpoints according to Arm ARM, return an error > if userspace tries to set CTX_CMPS field to such value. > > Signed-off-by: Reiji Watanabe > --- > arch/arm64/kvm/sys_regs.c | 84 ++++++++++++++++++++++++++++++++++----- > 1 file changed, 73 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 772e3d3067b2..0faf458b0efb 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -626,6 +626,45 @@ static int validate_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, > return 0; > } > > +static bool id_reg_has_pmu(u64 val, u64 shift, unsigned int min) I would rename the function as the name currently is misleading. The function validate the val filed @shift againt @min > +{ > + unsigned int pmu = cpuid_feature_extract_unsigned_field(val, shift); > + > + /* > + * Treat IMPLEMENTATION DEFINED functionality as unimplemented for > + * ID_AA64DFR0_EL1.PMUVer/ID_DFR0_EL1.PerfMon. > + */ > + if (pmu == 0xf) > + pmu = 0; Shouldn't we simply forbid the userspace to set 0xF? > + > + return (pmu >= min); > +} > + > +static int validate_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > + const struct id_reg_info *id_reg, u64 val) > +{ > + unsigned int brps, ctx_cmps; > + bool vcpu_pmu, dfr0_pmu; > + > + brps = cpuid_feature_extract_unsigned_field(val, ID_AA64DFR0_BRPS_SHIFT); > + ctx_cmps = cpuid_feature_extract_unsigned_field(val, ID_AA64DFR0_CTX_CMPS_SHIFT); > + > + /* > + * Number of context-aware breakpoints can be no more than number of > + * supported breakpoints. > + */ > + if (ctx_cmps > brps) > + return -EINVAL; > + > + vcpu_pmu = kvm_vcpu_has_pmu(vcpu); > + dfr0_pmu = id_reg_has_pmu(val, ID_AA64DFR0_PMUVER_SHIFT, ID_AA64DFR0_PMUVER_8_0); > + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */ > + if (vcpu_pmu ^ dfr0_pmu) > + return -EPERM; > + > + return 0; > +} > + > static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg) > { > u64 limit = id_reg->vcpu_limit_val; > @@ -669,6 +708,23 @@ static void init_id_aa64isar1_el1_info(struct id_reg_info *id_reg) > id_reg->vcpu_limit_val &= ~PTRAUTH_MASK; > } > > +static void init_id_aa64dfr0_el1_info(struct id_reg_info *id_reg) > +{ > + u64 limit = id_reg->vcpu_limit_val; > + > + /* Limit guests to PMUv3 for ARMv8.4 */ > + limit = cpuid_feature_cap_perfmon_field(limit, ID_AA64DFR0_PMUVER_SHIFT, > + ID_AA64DFR0_PMUVER_8_4); > + /* Limit debug to ARMv8.0 */ > + limit &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); > + limit |= (FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6)); > + > + /* Hide SPE from guests */ > + limit &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); > + > + id_reg->vcpu_limit_val = limit; > +} > + > static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, > const struct id_reg_info *idr) > { > @@ -698,6 +754,14 @@ static u64 get_reset_id_aa64isar1_el1(struct kvm_vcpu *vcpu, > idr->vcpu_limit_val : (idr->vcpu_limit_val & ~PTRAUTH_MASK); > } > > +static u64 get_reset_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > + const struct id_reg_info *idr) > +{ > + return kvm_vcpu_has_pmu(vcpu) ? > + idr->vcpu_limit_val : > + (idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER))); > +} > + > static struct id_reg_info id_aa64pfr0_el1_info = { > .sys_reg = SYS_ID_AA64PFR0_EL1, > .ftr_check_types = S_FCT(ID_AA64PFR0_ASIMD_SHIFT, FCT_LOWER_SAFE) | > @@ -742,6 +806,14 @@ static struct id_reg_info id_aa64mmfr0_el1_info = { > .validate = validate_id_aa64mmfr0_el1, > }; > > +static struct id_reg_info id_aa64dfr0_el1_info = { > + .sys_reg = SYS_ID_AA64DFR0_EL1, > + .ftr_check_types = S_FCT(ID_AA64DFR0_DOUBLELOCK_SHIFT, FCT_LOWER_SAFE), > + .init = init_id_aa64dfr0_el1_info, > + .validate = validate_id_aa64dfr0_el1, > + .get_reset_val = get_reset_id_aa64dfr0_el1, > +}; > + > /* > * An ID register that needs special handling to control the value for the > * guest must have its own id_reg_info in id_reg_info_table. > @@ -753,6 +825,7 @@ static struct id_reg_info id_aa64mmfr0_el1_info = { > static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = { > [IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info, > [IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info, > + [IDREG_IDX(SYS_ID_AA64DFR0_EL1)] = &id_aa64dfr0_el1_info, > [IDREG_IDX(SYS_ID_AA64ISAR0_EL1)] = &id_aa64isar0_el1_info, > [IDREG_IDX(SYS_ID_AA64ISAR1_EL1)] = &id_aa64isar1_el1_info, > [IDREG_IDX(SYS_ID_AA64MMFR0_EL1)] = &id_aa64mmfr0_el1_info, > @@ -1604,17 +1677,6 @@ static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id) > val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), gic_lim); > } > break; > - case SYS_ID_AA64DFR0_EL1: > - /* Limit debug to ARMv8.0 */ > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); > - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6); > - /* Limit guests to PMUv3 for ARMv8.4 */ > - val = cpuid_feature_cap_perfmon_field(val, > - ID_AA64DFR0_PMUVER_SHIFT, > - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); > - /* Hide SPE from guests */ > - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); > - break; > case SYS_ID_DFR0_EL1: > /* Limit guests to PMUv3 for ARMv8.4 */ > val = cpuid_feature_cap_perfmon_field(val, > Eric