[U-Boot] [PATCH v2 4/5] rv1108: Make USB OTG functional

[Andy Yan <andy.yan@rock-chips.com>]

Hi:

On 2018/11/21 上午2:55, Otavio Salvador wrote:
> Like it is done for other Rockchip SoCs, introduce a board_usb_init()
> function so that USB OTG can be functional on rv1108 too.
>
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> ---
>
> Changes in v2: None
>
>   arch/arm/dts/rv1108.dtsi              | 45 ++++++++++++++-
>   arch/arm/mach-rockchip/Makefile       |  1 +
>   arch/arm/mach-rockchip/rv1108-board.c | 81 +++++++++++++++++++++++++++
>   3 files changed, 124 insertions(+), 3 deletions(-)
>   create mode 100644 arch/arm/mach-rockchip/rv1108-board.c


It's better to split dtsi and .c file

>
> diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
> index 23a44bfaca..215d885225 100644
> --- a/arch/arm/dts/rv1108.dtsi
> +++ b/arch/arm/dts/rv1108.dtsi
> @@ -121,8 +121,35 @@
>   	};
>   
>   	grf: syscon at 10300000 {
> -		compatible = "rockchip,rv1108-grf", "syscon";
> +		compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
>   		reg = <0x10300000 0x1000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		u2phy: usb2-phy at 100 {
> +			compatible = "rockchip,rv1108-usb2phy";
> +			reg = <0x100 0x0c>;
> +			clocks = <&cru SCLK_USBPHY>;
> +			clock-names = "phyclk";
> +			#clock-cells = <0>;
> +			clock-output-names = "usbphy";
> +			rockchip,usbgrf = <&usbgrf>;
> +			status = "disabled";
> +
> +			u2phy_otg: otg-port {
> +				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "otg-mux";
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			u2phy_host: host-port {
> +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "linestate";
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
>   	};
>   
>   	saradc: saradc at 1038c000 {
> @@ -141,6 +168,11 @@
>   		reg = <0x20060000 0x1000>;
>   	};
>   
> +	usbgrf: syscon at 202a0000 {
> +		compatible = "rockchip,rv1108-usbgrf", "syscon";
> +		reg = <0x202a0000 0x1000>;
> +	};
> +
>   	cru: clock-controller at 20200000 {
>   		compatible = "rockchip,rv1108-cru";
>   		reg = <0x20200000 0x1000>;
> @@ -200,12 +232,19 @@
>   	};
>   
>   	usb20_otg: usb at 30180000 {
> -		compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
> +		compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
>   			     "snps,dwc2";
>   		reg = <0x30180000 0x40000>;
>   		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> -		hnp-srp-disable;
> +		clocks = <&cru HCLK_OTG>;
> +		clock-names = "otg";
>   		dr_mode = "otg";
> +		g-np-tx-fifo-size = <16>;
> +		g-rx-fifo-size = <280>;
> +		g-tx-fifo-size = <256 128 128 64 32 16>;
> +		g-use-dma;
> +		phys = <&u2phy_otg>;
> +		phy-names = "usb2-phy";
>   		status = "disabled";
>   	};
>   
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 05706c472a..368302e1da 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -33,6 +33,7 @@ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
>   obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
>   obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
>   obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
> +obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o
>   endif
>   
>   obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
> diff --git a/arch/arm/mach-rockchip/rv1108-board.c b/arch/arm/mach-rockchip/rv1108-board.c
> new file mode 100644
> index 0000000000..3412f2c063
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rv1108-board.c
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2015 Google, Inc
> + */
> +
> +#include <common.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> +#include <usb.h>
> +#include <usb/dwc2_udc.h>
> +
> +static struct dwc2_plat_otg_data rv1108_otg_data = {
> +	.rx_fifo_sz	= 512,
> +	.np_tx_fifo_sz	= 16,
> +	.tx_fifo_sz	= 128,
> +};
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> +	const void *blob = gd->fdt_blob;
> +	bool matched = false;
> +	int node, phy_node;
> +	u32 grf_phy_offset;
> +	const char *mode;
> +
> +	/* find the usb_otg node */
> +	node = fdt_node_offset_by_compatible(blob, -1, "rockchip,rk3066-usb");
> +	while (node > 0) {
> +		mode = fdt_getprop(blob, node, "dr_mode", NULL);
> +		if (mode && strcmp(mode, "otg") == 0) {
> +			matched = true;
> +			break;
> +		}
> +
> +		node = fdt_node_offset_by_compatible(blob, node,
> +						     "rockchip,rk3066-usb");
> +	}
> +
> +	if (!matched) {
> +		debug("usb_otg device not found\n");
> +		return -ENODEV;
> +	}
> +
> +	rv1108_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> +
> +	node = fdtdec_lookup_phandle(blob, node, "phys");
> +	if (node <= 0) {
> +		debug("phys node not found\n");
> +		return -ENODEV;
> +	}
> +
> +	phy_node = fdt_parent_offset(blob, node);
> +	if (phy_node <= 0) {
> +		debug("usb phy node not found\n");
> +		return -ENODEV;
> +	}
> +
> +	rv1108_otg_data.phy_of_node = phy_node;
> +	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
> +
> +	/* find the grf node */
> +	node = fdt_node_offset_by_compatible(blob, -1,
> +					     "rockchip,rv1108-grf");
> +	if (node <= 0) {
> +		debug("grf node not found\n");
> +		return -ENODEV;
> +	}
> +
> +	rv1108_otg_data.regs_phy = grf_phy_offset + fdtdec_get_addr(blob, node,
> +								    "reg");
> +
> +	return dwc2_udc_probe(&rv1108_otg_data);
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> +	return 0;
> +}
> +#endif