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[87.176.185.225]) by smtp.gmail.com with ESMTPSA id z14-20020a170906944e00b006f38c33b6e3sm4125607ejx.68.2022.04.26.22.54.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Apr 2022 22:54:55 -0700 (PDT) Message-ID: Date: Wed, 27 Apr 2022 07:54:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 0/5] Add new SoC21 infrastructure Content-Language: en-US To: Alex Deucher , amd-gfx@lists.freedesktop.org References: <20220426185255.3039590-1-alexander.deucher@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= In-Reply-To: <20220426185255.3039590-1-alexander.deucher@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 26.04.22 um 20:52 schrieb Alex Deucher: > This adds GPU SoC infrastructure for asics which > use the soc21 design. The first two patches are > register headers which are too big for the mailing > list so I have omitted them. We really have to find a way to better compress those. Anyway series is Acked-by: Christian König > > Hawking Zhang (3): > drm/amdgpu: add mp v13_0_0 ip headers v7 > drm/amdgpu: add gc v11_0_0 ip headers v11 > drm/amdgpu: add nbio callback to query rom offset > > Likun Gao (1): > drm/amdgpu: add new write field for soc21 > > Stanley.Yang (1): > drm/amdgpu: add soc21 common ip block v2 > > drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 13 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 1 + > drivers/gpu/drm/amd/amdgpu/soc15_common.h | 8 + > drivers/gpu/drm/amd/amdgpu/soc21.c | 620 + > drivers/gpu/drm/amd/amdgpu/soc21.h | 30 + > .../include/asic_reg/gc/gc_11_0_0_default.h | 6114 +++ > .../include/asic_reg/gc/gc_11_0_0_offset.h | 11670 +++++ > .../include/asic_reg/gc/gc_11_0_0_sh_mask.h | 41635 ++++++++++++++++ > .../include/asic_reg/mp/mp_13_0_0_offset.h | 461 + > .../include/asic_reg/mp/mp_13_0_0_sh_mask.h | 682 + > 11 files changed, 61233 insertions(+), 3 deletions(-) > create mode 100644 drivers/gpu/drm/amd/amdgpu/soc21.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/soc21.h > create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h > create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h > create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h > create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_0_offset.h > create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_0_sh_mask.h >