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From: Richard Henderson <rth@twiddle.net>
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Date: Tue, 20 Sep 2016 16:35:25 -0700
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Subject: Re: [Qemu-devel] [PATCH RFC v1 04/29] target-arc: AND, OR, XOR, BIC,
 TST
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To: Michael Rolnik <mrolnik@gmail.com>, qemu-devel@nongnu.org

On 09/08/2016 03:31 PM, Michael Rolnik wrote:
> +int arc_gen_AND(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
> +{
> +    TCGv rslt = dest;
> +
> +    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
> +        rslt = tcg_temp_new_i32();
> +    }
> +
> +    tcg_gen_and_tl(rslt, src1, src2);
> +
> +    if (ctx->opt.f) {
> +        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
> +        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
> +    }
> +
> +    if (!TCGV_EQUAL(dest, rslt)) {
> +        tcg_gen_mov_tl(dest, rslt);
> +        tcg_temp_free_i32(rslt);
> +    }

There is no reason for this rslt temporary stuff.
Unlike with add & sub, src1 & src2 are not used after the operation, for any of 
the logical operations.


r~