From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dinh Nguyen Date: Mon, 25 Feb 2019 10:33:59 -0600 Subject: [U-Boot] [PATCH] ARM: cache: Fix incorrect bitwise operation In-Reply-To: <20190219004351.791-1-marex@denx.de> References: <20190219004351.791-1-marex@denx.de> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 2/18/19 6:43 PM, Marek Vasut wrote: > The loop implemented in the code is supposed to check whether the > PL310 operation register has any bit from the mask set. Currently, > the code checks whether the PL310 operation register has any bit > set AND whether the mask is non-zero, which is incorrect. Fix the > conditional. > > Signed-off-by: Marek Vasut > Cc: Dalon Westergreen > Cc: Dinh Nguyen > Cc: Tom Rini > Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot") > --- > arch/arm/lib/cache-pl310.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c > index 1296ba6efd..bbaaaa4157 100644 > --- a/arch/arm/lib/cache-pl310.c > +++ b/arch/arm/lib/cache-pl310.c > @@ -33,7 +33,7 @@ static void pl310_background_op_all_ways(u32 *op_reg) > /* Invalidate all ways */ > writel(way_mask, op_reg); > /* Wait for all ways to be invalidated */ > - while (readl(op_reg) && way_mask) > + while (readl(op_reg) & way_mask) > ; > pl310_cache_sync(); > } > Thanks for fixing this! Reviewed-by: Dinh Nguyen Dinh