From: Grzegorz Szymaszek <gszymaszek@short.pl>
To: u-boot@lists.denx.de
Cc: Grzegorz Szymaszek <gszymaszek@short.pl>,
Marcin Sloniewski <marcin.sloniewski@gmail.com>,
Patrice Chotard <patrice.chotard@foss.st.com>,
Patrick Delaunay <patrick.delaunay@foss.st.com>,
uboot-stm32@st-md-mailman.stormreply.com
Subject: [PATCH v2 4/5] arm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR mode
Date: Wed, 2 Jun 2021 19:09:13 +0200 [thread overview]
Message-ID: <bc5e2aaf93fab7d50203752d99279725c3c94ef5.1622651232.git.gszymaszek@short.pl> (raw)
In-Reply-To: <cover.1622651232.git.gszymaszek@short.pl>
Enable the SDMMC2 eMMC high-speed DDR mode as it is done in the
corresponding Linux kernel device tree.
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
Changes for v2:
- rebased on current master
- added a short commit message body
arch/arm/dts/stm32mp157c-odyssey-som.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi
index 583812f137..1510a5b364 100644
--- a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi
+++ b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi
@@ -274,6 +274,7 @@
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&vdd>;
+ mmc-ddr-3_3v;
status = "okay";
};
--
2.30.2
next prev parent reply other threads:[~2021-06-02 17:09 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-02 17:08 [PATCH v2 0/5] arm: dts: stm32mp157c-odyssey-som: sync SDMMC2 with Linux and TF‑A Grzegorz Szymaszek
2021-06-02 17:08 ` [PATCH v2 1/5] arm: dts: stm32mp157c-odyssey-som: fix the basic SDMMC2 properties Grzegorz Szymaszek
2021-06-18 7:59 ` Patrice CHOTARD
2021-06-02 17:09 ` [PATCH v2 2/5] arm: dts: stm32mp157c-odyssey-som: enable all SDMMC2 data lanes Grzegorz Szymaszek
2021-06-18 7:59 ` Patrice CHOTARD
2021-06-18 7:59 ` Patrice CHOTARD
2021-06-02 17:09 ` [PATCH v2 3/5] arm: dts: stm32mp157c-odyssey-som: set the SDMMC2 VQMMC supply Grzegorz Szymaszek
2021-06-18 7:59 ` Patrice CHOTARD
2021-06-18 8:00 ` Patrice CHOTARD
2021-06-02 17:09 ` Grzegorz Szymaszek [this message]
2021-06-03 7:35 ` [PATCH v2 4/5] arm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR mode Patrice CHOTARD
2021-06-18 8:00 ` [Uboot-stm32] " Patrice CHOTARD
2021-06-18 8:00 ` Patrice CHOTARD
2021-06-02 17:09 ` [PATCH v2 5/5] arm: dts: stm32mp157c-odyssey-som: enable SDMMC2 in SPL Grzegorz Szymaszek
2021-06-03 7:36 ` Patrice CHOTARD
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