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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id i11sm1885810pjs.44.2020.05.12.19.05.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 May 2020 19:05:01 -0700 (PDT) Subject: Re: [PATCH v3 02/16] target/arm: Create gen_gvec_{u,s}{rshr,rsra} To: Peter Maydell References: <20200508152200.6547-1-richard.henderson@linaro.org> <20200508152200.6547-3-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 12 May 2020 19:04:59 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/12/20 6:46 AM, Peter Maydell wrote: > +void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, > + int64_t shift, uint32_t opr_sz, uint32_t max_sz) > +{ > + static const TCGOpcode vecop_list[] = { > + INDEX_op_shri_vec, INDEX_op_sari_vec, INDEX_op_add_vec, 0 > + }; >  > Is there documentation somewhere of which vector operations don't > need to be listed in the vecop list? Here gen_srshr_vec() also > uses 'dupi_vec' and 'and_vec', which aren't listed, presumably > because we guarantee them to be implemented? (Hopefully we don't > encounter a future host vector architecture which breaks that > assumption :-)) Yes, though perhaps not perfectly easy to find: it's at the top of tcg-op-vec.c. Correct, that the logicals and mov/dupi etc are mandatory and should not be listed. Moreover, I assert that they are *not* listed, so we get a CONFIG_DEBUG_TCG check of this list both positive and negative. I'm going to hope that no future architecture is so irregular as to not implement logicals. ;-) Or even be as irregular as Intel. >> I think the VRSRA case needs the same "shift = -shift" as VRSHR. > > With this bug fixed, > Reviewed-by: Peter Maydell Thanks, fixed. r~