From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Wed, 23 Dec 2020 08:50:11 +0900
Subject: [v5 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver
In-Reply-To: <20201221164942.11640-10-elly.siew.chin.lim@intel.com>
References: <20201221164942.11640-1-elly.siew.chin.lim@intel.com>
 <CGME20201221165140epcas1p40ea257185aeb43e690187e553b908377@epcas1p4.samsung.com>
 <20201221164942.11640-10-elly.siew.chin.lim@intel.com>
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On 12/22/20 1:49 AM, Siew Chin Lim wrote:
> From: Chee Hong Ang <chee.hong.ang@intel.com>
> 
> In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
> provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

Best Regards,
Jaehoon Chung


> 
> ---
> v5
> ---
> Call secure register access helper function to write the secure register.
> Return error if fail to write the secure register.
> ---
>  drivers/mmc/socfpga_dw_mmc.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> index 0a2845bcc2..7a485b492d 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -6,6 +6,7 @@
>  #include <common.h>
>  #include <log.h>
>  #include <asm/arch/clock_manager.h>
> +#include <asm/arch/secure_reg_helper.h>
>  #include <asm/arch/system_manager.h>
>  #include <clk.h>
>  #include <dm.h>
> @@ -13,6 +14,7 @@
>  #include <errno.h>
>  #include <fdtdec.h>
>  #include <dm/device_compat.h>
> +#include <linux/intel-smc.h>
>  #include <linux/libfdt.h>
>  #include <linux/err.h>
>  #include <malloc.h>
> @@ -58,10 +60,22 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
>  
>  	debug("%s: drvsel %d smplsel %d\n", __func__,
>  	      priv->drvsel, priv->smplsel);
> +
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> +	int ret;
> +
> +	ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
> +					 sdmmc_mask);
> +	if (ret) {
> +		printf("DWMMC: Failed to set clksel via SMC call");
> +		return ret;
> +	}
> +#else
>  	writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
>  
>  	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
>  		readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
> +#endif
>  
>  	/* Enable SDMMC clock */
>  	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
>